ROM BIOS & POST

Presented by
R.Annapoorani
S.Ranjani
B.Tech-IT
Pondicherry Engineering College

 Commonly known as the system BIOS or ROM
BIOS is a de facto standard defining a
firmware interface
 The BIOS software is built into the PC, and is
the first software run by a PC when powered
on
 Initializes and tests the system hardware
components, and loads an OS or other
program from a mass memory device.

 Invented by Gary Kildall in 1976
 Describes the machine-specific part of CP/M
 Later versions of CP/M come with an XIOS
instead of the BIOS.
 Most versions of DOS have a file called
"IO.SYS", "IBMBIO.COM", "IBMBIO.SYS", or
"DRBIOS.SYS”

 Check the CMOS Setup for custom settings
 Load the interrupt handlers and device
drivers
 Initialize registers and power management
 Perform the power-on self-test (POST)
 Display system settings
 Determine which devices are bootable
 Initiate the bootstrap sequence

 BIOS checks the information stored in a tiny
(64 bytes) amount of RAM located on a
(CMOS) chip.
 CMOS Setup provides detailed information
particular to your system
 The BIOS uses this information to modify or
supplement its default programming as
needed

 Interrupt handlers are small pieces of S/W
that act as translators b/w the H/W
components & the OS.
 The device drivers are other pieces of S/W
that identify the base H/W components
 Since the BIOS is constantly intercepting
signals to and from the hardware, it is
usually copied, or shadowed, into RAM to run
faster.

 When the processor is reset, it initializes its
program counter to a fixed.
 The BIOS ROM chips are located in memory so
that this starting address is within the BIOS.
 A jump instruction then directs the processor to
start executing code in the BIOS.
 If the system has just been powered up POST is
run.
 If a powered-up computer has had its reset key
pressed , a special flag value is detected in
memory and the BIOS does not run the POST.

 Selects candidate boot devices using
information collected by POST and
configuration information from EEPROM,
CMOS RAM or, in the earliest PCs, DIP
switches.
 The BIOS checks each device in order to see
if it is bootable.
 The BIOS proceeds to test each device
sequentially until a bootable device is found.

 In the IBM PC and AT, certain peripheral cards
carried their own BIOS extension option ROM
 BIOS extension ROMs, are executed before
the operating system is loaded from mass
storage.
 These ROMs can test and initialize hardware,
add BIOS services, or replace BIOS services
programmed in the motherboard

 The CPU is in real mode
 The general-purpose and segment registers
are undefined.
 The memory below address 500 hex contains
the interrupt vector table and the 256-byte
BIOS data area
 The interrupt vectors corresponding to the
BIOS interrupts have been set to point at the
appropriate entry points in the BIOS.

 The BIOS in the IBM PC and XT had no built-in
user-interface. The BIOS versions in earlier
PCs (XT-class) were not software
configurable
 But a modern BIOS has a user interface (UI),
typically a menu system accessed by pressing
a certain key on the keyboard when the PC
starts.

In the BIOS UI, a user can:
 Configure hardware
 Set the system clock
 Enable or disable system components
 Select which devices are potential boot
devices
 set various password prompts

 32 pin DIP chip.
 2Mb (256KB) in size.
 Hardware-
independent module,
that describes the
loading period of his
operating system.

Functions
The BIOS chip starts up the computer, loads
basic drivers, loads the operating system,
checks hardware systems, and loads other BIOS
programs on the computer.
Features
The first instructions run by a computer are
those from the BIOS chip. The internal clock of
a computer runs off the BIOS chip.

 Some BIOS chips allow overclocking, an
action in which the CPU is adjusted to a
higher clock rate than its factory preset.
 Overclocking may, compromise system
reliability in insufficiently cooled computers
 Overclocking, incorrectly performed, may
also cause components to overheat so quickly
that they destroy themselves.

 Search "System Information" from the Start
menu, then open the program.
 Click on the System Summary section on left-
hand side of the window, which will bring up
system information on the right-hand side of
the window.
 Check the line reading "Bios Version/Date" to
see the current BIOS version.

 The BIOS is stored in rewritable memory,
allowing the contents to be replaced or
'rewritten'. This rewriting of the contents
is termed flashing.
 Done by a special program, usually
provided by the system's manufacturer, or
at POST, with a BIOS image in a hard drive
or USB flash drive.
 A file containing such contents is
sometimes termed 'a BIOS image'.

Flashing the bios:
 Can correct bugs or compatibility that
have been discovered
 Increases system stability
 Enhances Storage Capacity

 Large hard drive support
 ACPI compatibility
 CPU support
 Fix problems
 Memory support

 The disadvantages are that the BIOS often boots
in 16-bit real mode & because of the type of
chip used, it is not always the fastest.
 BIOS routines are generally inefficient, so
modern OSs have their own hardware routines
and depend on drivers.
 Some BIOSes still have the initial types of bugs
from the PC-XT days.
 BIOS EEPROMS can be overwritten or destroyed
by users when updating the BIOS.
 BIOS could become virus infected or overwritten
by viruses

The four known BIOS Virus attacks are:
 CIH, whose name matches the initials of its
creator, Chen Ing Hau in 1998
 It was able to erase flash ROM BIOS content
 Infected computers could no longer boot,
and people had to remove the flash ROM IC
from the motherboard and reprogram it.

 The second BIOS virus was a technique
presented by John Heasman.
 In 2006, at the Black Hat Security
Conference, he showed how to elevate
privileges and read physical memory, using
malicious procedures that replaced normal
ACPI functions stored in flash memory.

 The third BIOS virus was a technique called
"Persistent BIOS infection”in 2009
 Researchers Anibal Sacco and Alfredo Ortega,
demonstrated how to insert malicious code
into the decompression routines in the BIOS,
allowing for nearly full control of the PC at
start-up, even before the operating system is
booted.

 The fourth one is Mebromi
 Mebromi is a trojan which targets computers
with AwardBIOS, Microsoft Windows
 Mebromi installs a rootkit which infects the
master boot record.

 Refers to routines executed by
microprocessor as soon as the PC is powered
on.
 The routines are part of a device's pre-boot
sequence.
 Once POST completes successfully, bootstrap
loader code is invoked.
 Verifies whether hardware is free from
faults.
 On encountering an error, PC is halted with
an error message.
 POST routines are stored in ROM.

 POST vector starts from FFFF0
 First instruction is JUMP instruction to the
address fro where exactly the POST routine
starts.
 First instruction in POST routine is CLI
 The POST starts executing test programs

 Disable Interrupts using CLI instruction
 Set SF,CF,ZF and PF flags
 Verify whether each of these flags is set
 If any flag is not set, a HALT instruction at
address FE0AD is executed
 Write 1’s in all
registers:AX,DS,BX,ES,CX,SS,DX,SP,BP,SI & DI
 Verify the contents of DI
 Write all 0’s in AX register
 Verify whether DI has received all zeroes

 Disable NMI by outputting zero to NMI
register at port address X ‘0A0’
 Initialize DMA page register by outputting
zeroes at port address X ‘83’
 Disable color video by outputting zeroes to
mode control register at port address X ‘3D8’
 Disable monochrome display & set high
resolution mode by outputting X ’01;

 Program the PPI as follows:
1. Port A and Port B output vectors
2. Port C input port
 Binary pattern 10100101 is outputted to PPI
port B

 Output X’01’ on port A of PPI
 Give FE000 as the start address & enter
subroutine ROM checksum
 It performs XOR of contents of all locations
in 8k ROM
 If (checksum==0) the ROM contents are OK
 If (checksum≠0) it indicates failure of ROM
checksum test

 Output X ‘02’ on port A in PPI
 Output X ‘04’ on port X ‘08’ to disable DMA
controller
 Program the Timer 1 for mode 2
 Output zero as initial value to Timer 1
 Latch Timer 1
 Set an initial value in Timer 1
 Latch Timer 1 count
 Read Timer 1 count and if it counts too slow
or fast the POST halts the processor

 Tests DMA channel address registers
 Tests count registers in all channels in DMA
Controller chip,8237
 If there is an error the POST halts the
processor at FE12D

 Channel 0 of DMA controller is initialized
with appropriate start address and byte
count values
 It does memory refreshing when Timer 1
sends DMA request signal

 After initializing channel 0 for memory
refresh and starting the memory refresh, the
POST sets modes for DMA channel 2 and 3
I/0 EXPANSION BOX ENABLING
 Done by outputting X ‘01’ on port X ‘1302’

 The first location is written with a pattern
X ‘00’ and read back
 The POST repeats the above test for all
patterns X’01’ to X’FF’ on first location
 The POST tries 5 patterns namely
AA,FF,55,00,01 on first location
 The POST indicates two types of failures:
 The pattern written and pattern read are
different
 The pattern written and pattern read maybe
same but there is parity error during reading

 The POST finds out the total system memory
including motherboard RAM and RAM on
expansion boards
 The total program memory allowed is 640K
Bytes

 A portion of 16K DRAM can be used as stack
for the remaining POST programs
 The POST initializes the stack pointer and
stack segment register

 Programs the 8259 by issuing a set of control
words:ICW1,ICW2,ICW4
 In PC, 8259 is operated in 8086 mode not in
8085 mode
 No cascading
 Masks all interrupts by sending a mask
pattern FF to PIC

 Writes a temporary set of interrupt vectors in
the initial portion of the first 16K DRAM.
 Establishes “BIOS subroutine call interrupt
vectors”

 The DIP switch block contains 8 switches
 The POST reads the 8 switches & store the 8
bit pattern in a memory location
 The 8 switches are sensed by POST through
port C

 Configuration includes information of type of
display adapter attached
 Four possibilities are:
 No display adapter
 CGA in 40X30 mode
 CGA in 80X25 mode
 MDA for both MDA and CGA

 Failure is indicated by long-short-short
beeps.
 POST goes ahead with subsequent tests
 During Warm Boot, the POST skips the video
RAM test

 POST enables video
 Sets the mode by programming mode control
register
 POST stores blanks in reverse video form in
video corresponding to the top of the screen
 The horizontal bar display will stay only for a
few seconds

 Reads the CRT status port
 Verifies timing of video signal & horizontal
sync signal
 POST produces speaker beeps on sensing any
error

 Sets and Resets Interrupt Mask Register
 Looks for the presence of spurious interrupt
 POST displays error code 101 on CRT Monitor
on detecting error

 Checks
1. Whether Timer 0 interrupt occurs or not?
2. Is Timer 0 counting too slowly? i.e.,slow
interrupts
3. Is Timer 0 counting too fast? i.e.,fast interrupts

 Resets the keyboard
 Keyboard sends a scancode
 Keyboard interrupt is raised by keyboard
interface
 Then POST reads scancode through PPI Port A
 If scancode is other than X ‘AA’, the POST
displays an error message on CRT screen

 A data pattern X ’55 55’ is written on
expansion box adapter board
 Is same data is received from port, the
I/O box is present else it’s absent

 Same as first 16K DRAM Test
 Test patterns are AA,55,FF,01 and 00
 On detecting error, the POST displays a
detailed message on CRT screen giving the
following information:
 Failing location: Address
 Failing bits pattern

 BASIC ROM is present as four 8K ROMs in IBM
PC
 Detects the presence of BASIC ROM
 If present it performs checksum calculation
of contents of BASIC ROM
 If not, POST displays the failing ROM’S Start
address followed by the word ‘ROM’
Eg., F6000 ROM

 POST Detects the presence of parallel ports
by writing data on O/P data port & reading
through I/P data port
 If the data received is same, printer
controller is present
 If not, POST checks for next Parallel ports
SERIAL PORTS SET UP
 Checks for the presence of serial ports
 Updates Equipment Flag table

 Enables interrupt controller
 Checks for errors
 On detecting error , it gives 2 short beeps
and displays ERROR(RESUME=‘F1’ KEY)
 Gives one short beep indicating the
reliability test is successful

 POST enables NMI by removing mask from the
NMI register
 NMI will be generated by hardware if RAM
parity check error is present
 8088 is unaware Of external masking of NMI
by software

 Bootstrap is the process of loading a set of
instructions when a computer is first turned
on or booted.
 During the start-up process, diagnostic tests
are performed that set or check
configurations and implement routine testing
for the connection of peripherals, hardware
and external memory devices.
 The bootloader or bootstrap program is then
loaded to initialize the OS.

 100-199 Motherboard
 200-299 RAM or Memory
 300-399 Keyboard
 400-499 Video Mono
 500-599 Video Color
 600-699 Floppy Drive
 700-799 Math Co-Processor
 900-999 LPT1
 1000-1099 LPT2
 1100-1199 COM 1
 1200-1299 COM 2
 17xx Hard Disk Controller
 3xxx NIC
 86xx Mouse

Beep Meaning
1 short beep Normal POST – system is OK
2 short beeps POST error – error code shown on
screen
No beep
Power supply, system board problem,
disconnected CPU, or disconnected
speaker
Continuous beep
Power supply, system board,
or keyboard problem
Repeating short beeps
Power supply or system board problem
or keyboard
1 long, 1 short beep System board problem
1 long, 2 short beeps Display adapter problem (MDA, CGA)
1 long, 3 short beeps
Enhanced Graphics Adapter
problem (EGA)
3 long beeps 3270 keyboard card

Color Meaning
Red Bad ROM
Yellow
CPU Exception Before
Bootstrap Code is
Loaded
Green
Bad Chip RAM or fail
of Agnus Chip (check
seating of Agnus)
Black No CPU
White
Expansion passed
test successfully
Grey Turn on
Constant white Failure of CPU

ROM BIOS & POST

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