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![THE SPARC ARCHITECTURE
Presented By:
CSE 1 [Batch - D]
Taha Malampattiwala](https://image.slidesharecdn.com/thesunsparcarchitecture-160808222901/75/The-sunsparc-architecture-1-2048.jpg)
Uploaded byTaha Malampatti
The sunsparc architecture
The document presents an overview of the SPARC architecture, developed by Sun Microsystems, emphasizing its RISC-based design, scalability, and key features. It covers the architecture's principles, historical revisions, and components such as the integer unit, register windows, and floating-point unit. Additionally, it discusses the permission structure for licensing the architecture and the compatibility with various operating systems.
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The sunsparc architecture
- 1. THE SPARC ARCHITECTURE PresentedBy: CSE 1 [Batch - D] Taha Malampattiwala
- 2. Outline INTRODUCTION RISC Design and Background Design principles DESIGN GOALS HISTORY THE SPARC ARCHITECTURE • Integer Unit (IU) • The Register Window • Floating Point Unit (FPU) • Coprocessor CORE PIPELINE INSTRUCTIONS LICENSE SPARC V9 FEATURES OPERATING SYSTEM SUPPORT REFERENCES
- 3. RISC: Defintion &Background • Reduced Instruction Set Computing, also called “load-store architecture” (due to the load-store instructions for accessing memory). • In the 1970's researchers noticed that a promising alternative to providing a large set of instructions to the ISA (instruction set arch.) would be to support only the most frequently used instructions, leaving the scarcely used instructions to be implemented by these as instruction sequences.
- 4. RISC: Design Principles •Simple instructions and few addressing modes – Extra stuff left out saves space for other things • Instructions conform to a simple format – Reduces decoding delays • Load-store design – Everything operates on registers only; load from memory to the large number of registers first, then manipulate the registers only; store to memory when done. • Hardwired control—no microcode – No translation from machine instructions, freeing CPU cycles needed to perform an instruction. – Also frees up chip space. • Goal: Execute one instruction per clock cycle – Uses pipelining and other features/principles described to get there. • Simplicity to facilitate the use of higher frequency clock cycles
- 5. Introduction SPARC standsfor Scalable Processor Architecture. It was developed by Sun Microsystems in the 1980s. It is based on the RISC structure designed at the University of California at Berkeley in early 1980s. The SPARC architecture is a non-proprietary architecture that any person or company can license and use to develop microprocessors and other semiconductor devices based on published industry standards. In 1989, Sun Microsystems transferred ownership of the SPARC specifications to an independent, non-profit organization, SPARC International, which administers and licenses the technology and provides conformance testing and other services for its members.
- 6. Design Goals SPARCwas designed as a target for optimizing compilers and easily pipelined hardware implementations. SPARC implementations provide exceptionally high execution rates(MIPS) and short time-to-market development schedules. Provide the scalability of the cost/performance ratio of successive implementations with the current improvements in circuit technology. The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from processors required in embedded systems to processors used for servers.
- 7. Brief History 3major revisions to the SPARC architecture - SPARC-V7, 32bit, 1986 - SPARC-V8, 32bit, 1990 - SPARC-V9, 64bit, 1993 Backward binary compatibility between them. In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005.
- 8. The SPARC Architecture It is a Load and store architecture. Operations are always done over registers. Uses “register window” concept thus offering a large number of registers. Uses delay slot to optimize branch instruction. Passes arguments using registers and the stack.
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- 11. The Integer Unit(IU) Contains the general purpose registers and controls the overall operation of the processor. may contain from 64 to 528 general-purpose 64-bit r registers. They are partitioned into 8 global registers, 8 alternate global registers, plus a circular stack of from 3 to 32 sets of 16 registers each, known as register windows. Executes the integer arithmetic instructions and computes memory addresses for loads and stores. Maintains the program counters and controls instruction execution for the FPU.
- 12. The Register Window At any time, an instruction can access the 8 global registers and a 24- register window A register window comprises a 16-register set- divided into 8 in and 8 local registers- together with the 8 in registers of an adjacent register set, addressable from the current window as its out registers. When a procedure is called, the register window shifts by sixteen registers, hiding the old input registers and old local registers and making the old output registers the new input registers. Input registers : arguments are passed to a function Local registers : to store any local data. Output registers : When calling a function, the programmer puts his argument in these registers.
- 13. The Register Window The current window into the r registers is given by the current window pointer (CWP) register.
- 14. The Floating-point Unit(FPU) The FPU has 32 32-bit (single-precision) floating-point registers, 32 64- bit (double-precision) floating-point registers, and 16 128-bit (quad- precision) floating-point registers. Double-precision values occupy an even-odd pair of single-precision registers. Quad-precision values occupy an odd-even number pair of double precision registers. Floating-point load/store instructions are used to move data between the FPU and memory. The memory address is calculated by the IU. Floating-Point operate (FPop) instructions perform the floating-point arithmetic operations and comparisons.
- 15. Coprocessor Unit (CU) The instruction set includes support for a single, implementation-dependent coprocessor. The coprocessor has its own set of registers. Coprocessor load/store instructions are used to move data between the coprocessor registers and memory. floating-point instructions mirrors coprocessor instructions. Not implemented in SPARC V9.
- 16. Instructions Instructions can fallinto following basic categories : Load/store Arithmetic/logical/shift Control transfer Read/write control register Floating-point/Coprocessor operate
- 17. • Afara Websystems •Bipolar Integrated Technology (BIT) • C-Cube • Cypress Semiconductor • Fujitsu and Fujitsu Microelectronics • HAL Computer Systems • Hyundai • LSI Logic • Magnum Semiconductor • Meiko Scientific • Metaflow Technologies • Prisma • Ross Technology • Parsé Semiconductor Co. • Solbourne Computer • WeitekThe The SPARC architecture has been licensed to many companies who have developed and fabricated implementations, such as:
- 18. SPARC v9 features 64-bit Data and Addresses as compared to 32-bit Data and Addresses of SPARC V8. 32 double-precision floating-point registers, Software-settable branch prediction 64-bit integer multiply and divide instructions load/store floating-point quad word instructions Branches on register value (eliminating the need to compare) The V9 remains binary compatible with all previous SPARC architecture.
- 19. Operating System Support Operating system support. SPARC machines have generally used Sun's SunOS, Solaris, OpenSolaris or derived as Illumos, but other operating systems such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux have also been used. In 1993, Intergraph announced a port of Windows NT to the SPARC architecture, but it was later cancelled. In October 2015, Oracle announced a "Linux for SPARC reference platform".
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