Tlc5940 ep

TLC5940-EP
www.ti.com SLVSA51D –MARCH 2010–REVISED MAY 2010
16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL
Check for Samples: TLC5940-EP
1FEATURES APPLICATIONS
• Monocolor, Multicolor, Full-Color LED Displays 2• 16 Channels
• 12-Bit (4096 Steps) Grayscale PWM Control • LED Signboards
• Dot Correction • Display Backlighting
– 6 Bit (64 Steps) • General, High-Current LED Drive
– Storable in Integrated EEPROM SUPPORTS DEFENSE, AEROSPACE,
• Drive Capability (Constant-Current Sink) of AND MEDICAL APPLICATIONS
0 mA to 72 mA (–40°C to 125°C) • Controlled Baseline
– 0 mA to 60 mA (VCC < 3.6 V, –40°C to 85°C) • One Assembly/Test Site
– 0 mA to 120 mA (VCC > 3.6 V, –40°C to 85°C) • One Fabrication Site
• LED Power Supply Voltage up to 17 V • Available in Q-Temp (–40°C/125°C)
• VCC = 3 V to 5.5 V • Extended Product Life Cycle
• Serial Data Interface • Extended Product-Change Notification
• Controlled In-Rush Current • Product Traceability
• 30-MHz Data Transfer Rate
• CMOS Level I/O
• Error Information
– LOD: LED Open Detection
– TEF: Thermal Error Flag
DESCRIPTION
The TLC5940 is a 16-channel, constant-current sink LED driver. Each channel has an individually adjustable
4096-step grayscale PWM brightness control and a 64-step, constant-current sink (dot correction). The dot
correction adjusts the brightness variations between LED channels and other LED drivers. The dot correction
data is stored in an integrated EEPROM. Both grayscale control and dot correction are accessible via a serial
interface. A single external resistor sets the maximum current value of all 16 channels.
The TLC5940 features two error information circuits. The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal error flag (TEF) indicates an overtemperature condition.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Delay
x0
12−Bit Grayscale
PWM Control
GS Register
DC Register
DC EEPROM
Constant Current
Driver
6−Bit Dot
Correction
LED Open Detection
Max. OUTn
Current
Temperature
Error Flag
(TEF)
Delay
x1
12−Bit Grayscale
PWM Control
GS Register
DC Register
6 11
DC EEPROM
Constant Current
Driver
6−Bit Dot
Correction
LED Open Detection
Delay
x15
12−Bit Grayscale
PWM Control
6−Bit Dot
5
6 11
GS Register
DC Register
DC EEPROM
Constant Current
Driver
LED Open Detection
OUT0
OUT1
OUT15
SCLK SIN
SOUT
IREF
XERR
XLAT
GSCLK
BLANK
DCPRG
DCPRG
1
DCPRG
VPRG
VPRG
VPRG
VCC GND
VPRG
Input
Shift
Register
Input
Shift
Register
1 0
VPRG 0 11
12 23
180 191
90 95
VPRG
0
0
95
96
191
LED Open
Detection
(LOD)
5
90 95
DCPRG
0
192
96
1 0
1 0 0
GS Counter CNT
CNT
CNT
CNT
96
96
Status
Information:
LOD,
TED,
DC DATA
192
0
191
1
0
1
0
VREF =1.24 V
Correction
1 0
Blank
TLC5940-EP
SLVSA51D –MARCH 2010–REVISED MAY 2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TA PACKAGE(1) PART NUMBER
28-pin HTSSOP PowerPAD™ TLC5940QPWPREP
–40°C to 125°C
32-pin 5mm x 5mm QFN TLC5940QRHBREP
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TLC5940-EP

TLC5940-EP
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
RHB PWP
THERMAL METRIC(1) UNIT
32 PINS 28 PINS
qJA Junction-to-ambient thermal resistance(2) 33.9 35.4 °C/W
qJC(TOP) Junction-to-case (top) thermal resistance(3) 30 24.94 °C/W
qJC(BOTTOM) Junction-to-case (bottom) thermal resistance(4) 3.9 5.37 °C/W
qJB Junction-to-board thermal resistance(5) 9.3 15.02 °C/W
ΨJT Junction-to-top characterization parameter(6) 0.619 1.297 °C/W
ΨJB Junction-to-board characterization parameter(7) 9.3 10.96 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction to case (bottom) thermal resistance is obtained by simulations of this device as configured per MilStd 883 method 1012.1.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-board characterization parameter, ΨJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
ABSOLUTE MAXIMUM RATINGS.
over operating free-air temperature range (unless otherwise noted)(1) (2)
UNIT
VI Input voltage range(3) VCC –0.3V to 6V
IO Output current (dc) 130mA
VI Input voltage range V(BLANK), V(DCPRG), V(SCLK), V(XLAT), V(SIN), V(GSCLK), V(IREF) –0.3V to VCC +0.3V
V(SOUT), V(XERR) –0.3V to VCC +0.3V
VO Output voltage range
V(OUT0) to V(OUT15) –0.3V to 18V
EEPROM program range V(VPRG) –0.3V to 24V
EEPROM write cycles 25
HBM (JEDEC JESD22-A114, Human Body Model) 2kV
ESD rating
CBM (JEDEC JESD22-C101, Charged Device Model) 500V
Tstg Storage temperature range –55°C to 150°C
TA Operating ambient temperature range –40°C to 125°C
Package thermal impedance See Thermal Characteristics table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See www.ti.com/ep_quality for additional information on enhanced plastic packaging.
(3) All voltage values are with respect to network ground terminal.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3

1.00E+04
1.00E+03
1.00E+02
1.00E+01
1.00E+00
Notes:
1. See datasheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include
package interconnect life).
3. Enhanced plastic product disclaimer applies.
100 110 120 130 140 150 160
Continuous TJ (°C)
Estimated Life (Years)
Wirebond Voiding
Fail Mode (PWP)
Wirebond Voiding
Fail Mode (RHB)
TLC5940-EP
Figure 1. TLC5940-EP Mold Compound Operating Life

TLC5940-EP
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
DC CHARACTERISTICS
VCC Supply Voltage 3 5.5 V
V O Voltage applied to output (OUT0–OUT15) 17 V
VIH High-level input voltage 0.8 VCC VCC V
V GND 0.2 IL Low-level input voltage V V CC
IOH High-level output current VCC = 5V at SOUT –1 mA
IOL Low-level output current VCC = 5V at SOUT 1 mA
–40°C to 125°C 72
IOLC Constant output current OUT0 to OUT15 –40°C to 85°C, VCC < 3.6 V 60 mA
–40°C to 85°C, VCC > 3.6 V 120
V(VPRG) EEPROM program voltage 20 22 23 V
TA Operating free-air temperature range -40 125 °C
AC CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = –40°C to 125°C (unless otherwise noted)
f(SCLK) Data shift clock frequency SCLK 30 MHz
f(GSCLK) Grayscale clock frequency GSCLK 30 MHz
twh0/twl0 SCLK pulse duration SCLK = H/L (see Figure 12) 16 ns
twh1/twl1 GSCLK pulse duration GSCLK = H/L (see Figure 12) 16 ns
twh2 XLAT pulse duration XLAT = H (see Figure 12) 20 ns
twh3 BLANK pulse duration BLANK = H (see Figure 12) 20 ns
tsu0 SIN to SCLK ↑(1) (see Figure 12) 5 ns
tsu1 SCLK ↓ to XLAT ↑ (see Figure 12) 10 ns
tsu2 VPRG ↑ ↓ to SCLK ↑ (see Figure 12) 10 ns
tsu3 Setup time VPRG ↑ ↓XLAT ↑ (see Figure 12) 10 ns
tsu4 BLANK ↓ to GSCLK ↑ (see Figure 12) 10 ns
tsu5 XLAT ↑ to GSCLK ↑ (see Figure 12) 30 ns
tsu6 VPRG ↑ to DCPRG ↑ (see Figure 17) 1 ms
th0 SCLK ↑ to SIN (see Figure 12) 3 ns
th1 XLAT ↓ to SCLK ↑ (see Figure 12) 10 ns
th2 SCLK ↑ to VPRG ↑ ↓ (see Figure 12) 10 ns
Hold Time
th3 XLAT ↓ to VPRG ↑ ↓ (see Figure 12) 10 ns
th4 GSCLK ↑ to BLANK ↑ (see Figure 12) 10 ns
th5 DCPRG ↓ to VPRG ↓ (see Figure 12) 1 ms
tprog Programming time for EEPROM (see Figure 17) 20 ms
(1) ↑ and ↓ indicates a rising edge, and a falling edge respectively.
DISSIPATION RATINGS
PACKAGE POWER RATING DERATING FACTOR POWER RATING POWER RATING POWER RATING TA < 25°C ABOVE TA = 25°C TA = 70°C TA = 85°C TA = 125°C
28-pin HTSSOP with 3958mW 31.67mW/°C 2533mW 2058mW 791mW PowerPAD™ soldered(1)
28-pin HTSSOP with 2026mW 16.21mW/°C 1296mW 1053mW 405mW
PowerPAD™ unsoldered
32-pin QFN(1) 3482mW 27.86mW/°C 2228mW 1811mW 696mW
(1) The PowerPAD is soldered to the PCB with a 2 oz. (56,7 grams) copper trace. See SLMA002 for further information.

TLC5940-EP
ELECTRICAL CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -1mA, SOUT VCC –0.5 V
VOL Low-level output voltage IOL = 1mA, SOUT 0.5 V
VI = VCC or GND; BLANK, DCPRG, GSCLK, SCLK, SIN, XLAT –1 1
V mA II Input current I = GND; VPRG –2 2
VI = VCC; VPRG 50
VI = 21V; VPRG; DCPRG = VCC 4 10 mA
No data transfer, all output OFF, 0.9 6 VO = 1V, R(IREF) = 10kΩ
No data transfer, all output OFF, 5.2 12 VO = 1V, R(IREF) = 1.3kΩ
ICC Supply current mA
Data transfer 30MHz, all output ON, 16 VO = 1V, R(IREF) = 1.3kΩ
Data transfer 30MHz, all output ON, 30 VO = 1V, R(IREF) = 640Ω
Constant sink current (see All output ON, VO = 1V, R(IREF) = 640Ω, 25°C 54 61 69 IO(LC) Figure 3) mA All output ON, VO = 1V, R(IREF) = 640Ω, Full temperature 42 61 72
I All output OFF, VO = 15V, R(IREF) = 640Ω, lkg Leakage output current OUT0 to OUT15 ±1 mA
All output ON, VO = 1V, R(IREF) = 640Ω,
±4
OUT0 to OUT15, 25°C
±12
Constant sink current error OUT0 to OUT15(1), Full temperature ΔIO(LC0) (see Figure 3) % All output ON, VO = 1V, R(IREF) = 1300Ω,
±4
OUT0 to OUT15, 25°C
±8
OUT0 to OUT15(1), Full temperature
Δ Constant sink current error Device to device, Averaged current from OUT0 to –2 IO(LC1) (see Figure 3) OUT15, R % (IREF) = 1920Ω (20mA)(2) +0.4
Δ Constant sink current error Device to device, Averaged current from OUT0 to –2.7 IO(LC2) (see Figure 3) OUT15, R % (IREF) = 480Ω (80mA)(2) +2
All output ON, VO = 1V, R(IREF) = 640Ω ±4
OUT0 to OUT15(3), 25°C
All output ON, VO = 1V, R(IREF) = 640Ω ±11
ΔIO(LC3) Line regulation (see Figure 3) %/V
All output ON, VO = 1V, R(IREF) = 1300Ω , ±4 OUT0 to OUT15(3), 25°C
All output ON, VO = 1V, R(IREF) = 1300Ω , ±4 OUT0 to OUT15(3), Full temperature
All output ON, VO = 1V to 3V, R(IREF) = 640Ω,
±6
OUT0 to OUT15(4), 25°C
All output ON, VO = 1V to 3V, R(IREF) = 640Ω,
±20
ΔIO(LC4) Load regulation (see Figure 3) %/V
All output ON, VO = 1V to 3V, R(IREF) = 1300Ω, ±6 OUT0 to OUT15(4), 25°C
All output ON, VO = 1V to 3V, R(IREF) = 1300Ω, ±6 OUT0 to OUT15(4), Full temperature
(1) The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Table 1.
(2) The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Table 1.
The ideal current is calculated by Equation 3 in Table 1.
(3) The line regulation is calculated by Equation 4 in Table 1.
(4) The load regulation is calculated by Equation 5 in Table 1.

100
I I
OUTn OUTavg _ 0 15
I
(%)
OUTavg _ 0 15
´
-
D =
-
-
100
I I
OUTavg OUT(IDEAL)
I
(%)
OUT(IDEAL)
´
-
D =
ö
÷ ÷
ø
æ
ç ç
è
= ´
1.24V
IREF
I 31.5
OUT(IDEAL) R
100
2.5
(I at V = 5.5V) - (I at V =
3.0V)
OUTn CC OUTn CC ´
(I at V 3.0V)
(%/ V)
OUTn CC
=
D =
100
2.0
(I at V = 3.0V) - (I at V =
1.0V)
OUTn OUTn OUTn OUTn ´
(I at V 1.0V)
(%/ V)
OUTn OUTn
=
D =
TLC5940-EP
ELECTRICAL CHARACTERISTICS (continued)
T(TEF) Thermal error flag threshold Junction temperature(5) 150 170 °C
V(LED) LED open detection threshold 0.3 0.4 V
V Reference voltage (IREF) output R(IREF) = 640Ω 1.20 1.24 1.28 V
(5) Not tested. Specified by design
Table 1. Test Parameter Equations
(1)
(2)
(3)
(4)
(5)
SWITCHING CHARACTERISTICS
VCC = 3V to 5.5V, TA = -40°C to 125°C (unless otherwise noted)
tr0 SOUT 16
Rise time ns
tr1 OUTn, VCC = 5V, TA = 60°C, DCn = 3Fh 10 30
tf0 SOUT 16
Fall time ns
tf1 OUTn, VCC = 5V, TA = 60°C, DCn = 3Fh 10 30
tpd0 SCLK to SOUT (see Figure 12) 30 ns
tpd1 BLANK to OUT0 60 ns
tpd2 OUTn to XERR (see Figure 12 ) 1000 ns
Propagation delay time
tpd3 GSCLK to OUT0 (see Figure 12 ) 60 ns
tpd4 XLAT to IOUT (dot correction) (see Figure 12 ) 60 ns
tpd5 DCPRG to OUT0 (see Figure 12) 30 ns
td Output delay time OUTn to OUT(n+1) (see Figure 12 ) 20 30 ns
ton-err Output on-time error touton– Tgsclk (see Figure 12), GSn = 01h, GSCLK = 11 MHz 10 –50 –90 ns

THERMAL
PAD
GSCLK 24
SOUT 23
XERR 22
OUT15 21
OUT14 20
OUT13 19
OUT12 18
OUT11 17
16 OUT10
15 OUT9
14 OUT8
13 NC
12 NC
11 OUT7
10 OUT6
9 OUT5
OUT4 8
OUT3 7
OUT2 6
OUT1 5
OUT0 4
VPRG 3
SIN 2
SCLK 1
DCPRG 25
IREF 26
VCC 27
NC 28
NC 29
GND 30
BLANK 31
XLAT 32
RHB PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
BLANK
XLAT
SCLK
SIN
VPRG
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
DCPRG
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
PWP PACKAGE
(TOP VIEW)
Thermal
PAD
TLC5940-EP
DEVICE INFORMATION

TLC5940-EP
TERMINAL FUNCTION
TERMINAL
NO. I/O DESCRIPTION
NAME
PWP RHB
BLANK 2 31 I Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also reset. When BLANK = L, OUTn are controlled by grayscale PWM control.
Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H, DC is
DCPRG 26 25 I connected to the DC register.
DCPRG also controls EEPROM writing, when VPRG = V(PRG). EEPROM data = 3Fh (default)
GND 1 30 G Ground
GSCLK 25 24 I Reference clock for grayscale PWM control
IREF 27 26 I Reference current terminal
NC – 12, 13, No connection 28, 29
OUT0 7 4 O Constant current output
SCLK 4 1 I Serial data shift clock
SIN 5 2 I Serial data input
SOUT 24 23 O Serial data output
VCC 28 27 I Power supply voltage
Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, the
VPRG 6 3 I device is in DC mode. When VPRG = V(VPRG), DC register data can programmed into DC EEPROM
with DCPRG=HIGH. EEPROM data = 3Fh (default)
XERR 23 22 O Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.
Level triggered latch signal. When XLAT = high, the TLC5940 writes data from the input shift register
XLAT 3 32 I to either GS register (VPRG = low) or DC register (VPRG = high). When XLAT = low, the data in GS
or DC register is held constant.

INPUT EQUIVALENT CIRCUIT
(BLANK, XLAT, SCLK, SIN, GSCLK, DCPRG)
VCC
INPUT
GND
400 W
OUTPUT EQUIVALENT CIRCUIT (SOUT)
23 W
23
VCC
SOUT
GND
INPUT EQUIVALENT CIRCUIT (IREF)
_
+
Amp
400 W
100 W
VCC
INPUT
GND
OUTPUT EQUIVALENT CIRCUIT (XERR)
XERR
GND
23 W
INPUT EQUIVALENT CIRCUIT (VCC)
INPUT
GND
INPUT EQUIVALENT CIRCUIT (VPRG)
INPUT
GND
OUTPUT EQUIVALENT CIRCUIT (OUT)
OUT
GND
W
V(IREF)
TLC5940-EP
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Resistor values are equivalent resistances, and they are not tested.
Figure 2. Input and Output Equivalent Circuits

SOUT
tr0, tf0, tpd0 tr1, tf1, tpd1, tpd2, tpd3, tpd4, tpd5, td
OUTn
VO = 4V
Testpoint
CL = 15pF
R = 51W
L
Testpoint
CL = 15pF
VO = 1V
OUTn
VO = 1V to 3V
OUTn
IREF
Testpoint
R (IREG) 470k!
V(IREF)
VCC
XERR
tpd3
IO(LC), IO(LC0), IO(LC1), IO(LC2), IO(LC3)
D D D D DIO(LC4)
= 640W
TLC5940-EP
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Parameter Measurement Circuits

10 k
1 k
100
0 20 60 100
IO − Output Current − mA
W
Reference Resistor, R - (IREF)
40 80 120
7.68 k!
1.92 k!
0.96 k!
0.64 k!
0.38 k!
0.32 k!
0.48 k!
4 k
3 k
2 k
1 k
0
TLC5940PWP
PowerPAD Soldered
TLC5940RHB
TLC5940PWP
PowerPAD Unsoldered
-20 0 20 100
o
TA − Free-Air Temperature − C
Power Dissipation Rate - mW
-40 40 60 80
140
120
100
80
60
40
20
0
0 0.5 1 1.5 2 2.5 3
VO - Output Voltage - V
I - Output Current - mA O
T = 25 C,
V = 5 V
A
CC
° I = 120 mA O
IO = 100 mA
IO = 80 mA
IO = 60 mA
IO = 40 mA
IO = 20 mA
IO = 5 mA
65
64
63
62
61
60
59
58
57
56
55
0 0.5 1 1.5 2 2.5 3
VO - Output Voltage - V
I = 60 mA,
V = 5 V
O
CC TA = 85 °
C
TA = -40 °
C
TA = 25 °
C
TLC5940-EP
TYPICAL CHARACTERISTICS
REFERENCE RESISTOR POWER DISSIPATION RATE
vs vs
OUTPUT CURRENT FREE-AIR TEMPERATURE
Figure 4. Figure 5.
OUTPUT CURRENT OUTPUT CURRENT
vs vs
OUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 6. Figure 7.

8
6
4
2
0
-2
-4
-6
-8
0 20 40 60 80
IO - Output Current - mA
! I - Constant Output Current - % OLC
T = 25 C,
V = 5 V
A
CC
°
8
6
4
2
0
-2
-4
-6
-8
-40 -20 0 20 40 60 80 100
TA - Ambient Temperature - °
C
! I - Constant Output Current - % OLC
VCC = 3.3 V
VCC = 5 V
IO = 60 mA
140
120
100
80
60
40
20
0
IO = 120 mA
IO = 80 mA
IO = 60 mA
IO = 30 mA
0 10 20 30 40 50 60 70
Dot Correction Data - dec
IO = 5 mA
T = 25 C,
V = 5 V
A
CC
°
70
60
50
40
30
20
10
0
0 10 20 30 40 50 60 70
Dot Correction Data - dec
TA = -40 °
C
TA = 25 °
C
TA = 85 °
C
I = 60 mA,
V = 5 V
O
CC
TLC5940-EP
TYPICAL CHARACTERISTICS (continued)
CONSTANT OUTPUT CURRENT, ΔIOLC CONSTANT OUTPUT CURRENT, ΔIOLC
vs vs
AMBIENT TEMPERATURE OUTPUT CURRENT
Figure 8. Figure 9.
OUTPUT CURRENT OUTPUT CURRENT
vs vs
DOT CORRECTION LINEARITY (ABS VALUE) DOT CORRECTION LINEARITY (ABS VALUE)
Figure 10. Figure 11.

VPRG
XLAT
SIN
SCLK
SOUT
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
DC
MSB
DC
LSB
1 96
DC
MSB
1 192 193 1 192 193 1
t tsu4 h4
1 4096
twh3
1
GS1
MSB
GS1
LSB
GS1
MSB
GS2
MSB
GS2
LSB
GS2
MSB
SID2
MSB
SID2
MSB-1
SID1
MSB
SID1
MSB-1
SID1
LSB
GS3
MSB
- - -
twh2
tsu2 tsu1 twh0
twl0
tsu0
th0
tpd0
tpd1
tpd1 + td
tpd1 + 15 x td
tpd3
td
15 x td
tpd2
tpd3 + td
tpd3 tpd4
twl1
twh1
DC Data Input Mode GS Data Input Mode
1st GS Data Input Cycle 2nd GS Data Input Cycle
1st GS Data Output Cycle 2nd GS Data Output Cycle
tsu3
th3
th2
th1
tsu5
Tgsclk
touton
SIN(a) SIN SOUT SOUT(b)
TLC5940 (a)
BLANK,
GSCLK,
SIN SOUT
TLC5940 (b)
SCLK, XLAT,
DCPRG,
VPRG
TLC5940-EP
PRINCIPLES OF OPERATION
SERIAL INTERFACE
The TLC5940 has a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal
shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of XLAT
signal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLAT
signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on the
programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although
new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale
data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing
grayscale data. Figure 12 shows the timing chart. More than two TLC5940s can be connected in series by
connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two
TLC5940s is shown in Figure 13 and the timing chart is shown in Figure 14. The SOUT pin can also be
connected to the controller to receive status information from TLC5940 as shown in Figure 23.
Figure 12. Serial Data Input Timing Chart
Figure 13. Cascading Two TLC5940 Devices

VPRG
XLAT
SIN(a)
SCLK
SOUT(b)
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
1
192X2
DCb
MSB
DCa
LSB
DCb
MSB
1 384 385 1 384 385 1
1 4096 1
GSb1
MSB
GSa1
LSB
GSb1
MSB
GSb2
MSB
GSa2
LSB
GSb2
MSB
SIDb2
MSB
SIDb2
MSB-1
SIDb1
MSB
SIDb1
MSB-1
SIDa1
LSB
GSb3
MSB
192
96X2
- - -
TLC5940-EP
Figure 14. Timing Chart for Two Cascaded TLC5940 Devices
ERROR INFORMATION OUTPUT
The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normal
operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is
pulled up to VCC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned
on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and
pulled up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error
(see Figure 23).
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
Table 2. XERR Truth Table
ERROR CONDITION ERROR INFORMATION SIGNALS
TEMPERATURE OUTn VOLTAGE TEF LOD BLANK XERR
TJ < T(TEF) Don't Care L X H
H
TJ > T(TEF) Don't Care H X L
OUTn > V(LED) L L H
TJ < T(TEF) OUTn < V(LED) L H L
L
OUTn > V(LED) H L L
TJ > T(TEF) OUTn < V(LED) H H L
TEF: THERMAL ERROR FLAG
The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If
the junction temperature exceeds the threshold temperature (160°C typical), TEF becomes H and XERR pin
goes to low level. When the junction temperature becomes lower than the threshold temperature, TEF becomes
L and XERR pin becomes high impedance. TEF status can also be read out from the TLC5940 status register.

Imax
V(IREF)
R(IREF)
31.5
TLC5940-EP
LOD: LED OPEN DETECTION
The TLC5940 has an LED-open detector that detects broken or disconnected LEDs. The LED open detector
pulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in the Status
Information Data is only active under the following open-LED conditions.
1. OUTn is on and the time tpd2 (1 ms typical) has passed.
2. The voltage of OUTn is 0.3V (typical)
The LOD status of each output can be also read out from the SOUT pin. See STATUS INFORMATION OUTPUT
section for details. The LOD error bits are latched into the Status Information Data when XLAT returns to a low
after a high. Therefore, the XLAT pin must be pulsed high then low while XERR is active in order to latch the
LOD error into the Status Information Data for subsequent reading via the serial shift register.
DELAY BETWEEN OUTPUTS
The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant current
driver block of the device (see the functional block diagram). The fixed-delay time is 20ns (typical), OUT0 has no
delay, OUT1 has 20ns delay, and OUT2 has 40ns delay, etc. The maximum delay is 300ns from OUT0 to
OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large
inrush currents which reduces the bypass capacitors when the outputs turn on.
OUTPUT ENABLE
All OUTn channels of the TLC5940 can be switched off with one signal. When BLANK is set high, all OUTn
channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When
BLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back high
again in less than 300ns, all outputs programmed to turn on still turn on for either the programmed number of
grayscale clocks, or the length of time that the BLANK signal was low, which ever is lower. For example, if all
outputs are programmed to turn on for 1ms, but the BLANK signal is only low for 200ns, all outputs still turn on
for 200ns, even though some outputs are turning on after the BLANK signal has already gone high.
Table 3. BLANK Signal Truth Table
BLANK OUT0 - OUT15
LOW Normal condition
HIGH Disabled
SETTING MAXIMUM CHANNEL CURRENT
The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed between
IREF pin and GND pin. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of
1.24V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of
31.5. The maximum output current per channel can be calculated by Equation 6:
(6)
where:
V(IREF) = 1.24 V
R(IREF) = User-selected external resistor.
Imax must be set between 5 mA and 120 mA. The output current may be unstable if Imax is set lower than 5 mA.
Output currents lower than 5 mA can be achieved by setting Imax to 5 mA or higher and then using dot
correction.
Figure 4 shows the maximum output current IO versus R(IREF). R(IREF) is the value of the resistor between IREF
terminal to GND, and IO is the constant output current of OUT0 to OUT15. A variable power supply may be
connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum
output current per channel is 31.5 times the current flowing out of the IREF pin.

( ) ( x N)
P = V x I +
D CC CC
V x I
OUT MAX
x
DCn
63
x d
PWM
IOUTn ImaxDCn
63
TLC5940-EP
POWER DISSIPATION CALCULATION
The device power dissipation must be below the power dissipation rating of the device package to ensure correct
operation. Equation 7 calculates the power dissipation of device:
(7)
where:
VCC: device supply voltage
ICC: device supply current
VOUT: TLC5940 OUTn voltage when driving LED current
IMAX: LED current adjusted by R(IREF) Resistor
DCn: maximum dot correction value for OUTn
N: number of OUTn driving LED at the same time
dPWM: duty cycle defined by BLANK pin or GS PWM value
OPERATING MODES
The TLC5940 has operating modes depending on the signals DCPRG and VPRG. Table 4 shows the available
operating modes. The TPS5940 GS operating mode (see Figure 12) and shift register values are not defined
after power up. One solution to solve this is to set dot correction data after TLS5940 power-up and switch back
to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latch
it while TLS540 is in GS PWM mode. The values in the input shift register, DC register and GS register are
unknown just after power on. The DC and GS register values should be properly stored through the serial
interface before starting the operation.
Table 4. TLC5940 Operating Modes Truth Table
SIGNAL
INPUT SHIFT REGISTER MODE DC VALUE
DCPRG VPRG
L EEPROM
GND 192 bit Grayscale PWM Mode
H DC Register
L EEPROM
VCC 96 bit Dot Correction Data Input Mode
H DC Register
L EEPROM
H V(VPRG) X EEPROM Programming Mode Write dc register value to EEPROM. (Default
data: 3Fh)
SETTING DOT CORRECTION
The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently.
This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to
the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The
channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. Dot correction
for all channels must be entered at the same time. Equation 8 determines the output current for each output n:
(8)
where:
Imax = the maximum programmable output current for each output.
DCn = the programmed dot correction value for output n (DCn = 0 to 63).
n = 0 to 15

MSB LSB
0
DC 0.0
6
DC 1.0
90
DC 15.0
95
DC 15.5
5
DC 0.5
89
DC 14.5
DC OUT15 DC OUT14 − DC OUT2 DC OUT0
VPRG
SIN
SCLK 1 2 3 95 96 1 2
tsu1
DC n
MSB
DC n
MSB−1
DC n
MSB−2
DC n
LSB+1
DC n
LSB
DC n
MSB
DC n+1
MSB
DC n+1
MSB−1
DC n
MSB−1
DC n
MSB−2
DC n−1
LSB
DC n−1
LSB+1
DC n−1
MSB
DC n−1
MSB−1
DC n−1
MSB−2
SOUT
XLAT
DC Mode Data
Input Cycle n
DC Mode Data
V Input Cycle n+1 CC
twh0
twl0
DC n−1
LSB
twh2
th1
TLC5940-EP
Figure 15 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. The DC
15.5 in Figure 15 stands for the 5th most significant bit for output 15.
Figure 15. Dot Correction Data Packet Format
When VPRG is set to VCC, the TLC5940 enters the dot correction data input mode. The length of input shift
register becomes 96 bits. After all serial data are shifted in, the TLC5940 writes the data in the input shift register
to DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is a
level triggered latch of XLAT signal. Since XLAT is a level-triggered signal, SCLK and SIN must not be changed
while XLAT is high. After XLAT goes low, data in the DC register is latched and does not change. BLANK signal
does not need to be high to latch in new data. XLAT has setup time (tsu1) and hold time (th1) to SCLK as shown
in Figure 16.
Figure 16. Dot Correction Data Input Timing Chart
The TLC5940 also has an EEPROM to store dot correction data. To store data from the dot correction register to
EEPROM, DCPRG is set to high after applying VPRG to the VPRG pin. Figure 17 shows the EEPROM
programming timings. The EEPROM has a default value of all 1s.

VPRG
DCPRG
XLAT
SIN
SCLK
SOUT
1 96
DC
MSB
-
DC
MSB
DC
LSB
VCC
V(PRG)
tsu6 tprog th5
DCPRG
OUT0
(Current)
Figure 17. EEPROM Programming Timing Chart
tpd5 tpd5
OUT15
(Current)
SETTING GRAYSCALE
The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bits
per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 9 determines
the brightness level for each output n:
Brightness in % GSn
Figure 18. DCPRG and OUTn Timing Diagram
4095100
TLC5940-EP
MSB LSB
0
GS 0.0
12
GS 1.0
180
GS 15.0
191
GS 15.11
11
GS 0.11
179
GS 14.11
GS OUT15 GS OUT14 − GS OUT2 GS OUT0
(9)
where:
GSn = the programmed grayscale value for output n (GSn = 0 to 4095)
n = 0 to 15
Grayscale data for all OUTn
Figure 19 shows the grayscale data packet format which consists of 12 bits x 16 channels, totaling 192 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc.
Figure 19. Grayscale Data Packet Format
When VPRG is set to GND, the TLC5940 enters the grayscale data input mode. The device switches the input
shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into

MSB LSB
0 23
24 119 120
15 16
191
LOD 15 X DC 15.5 DC 0.0 X X
LOD Data DC Values Reserved
TEF
LOD 0 TEF
X
TLC5940-EP
the grayscale register (see Figure 12). New grayscale data immediately becomes valid at the rising edge of the
XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is
high.The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to
complete the grayscale update cycle. All GS data in the input shift register is replaced with status information
data (SID) after updated the grayscale register.
STATUS INFORMATION OUTPUT
The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG=GND).
After the XLAT signal latches the data into the GS register the input shift register data will be replaced with status
information data (SID) of the device (see Figure 19). LOD, TEF, and dot correction EEPROM data
(DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at SOUT pin. The status
information data packet is 192 bits wide. Bits 0-15 contain the LOD status of each channel. Bit 16 contains the
TEF status. If DCPRG is low, bits 24-119 contain the data of the dot-correction EEPROM. If DCPRG is high, bits
24-119 contain the data of the dot-correction register.The remaining bits are reserved. The complete status
information data packet is shown in Figure 20.
SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown Figure 21.
The next SCLK pulse, which will be the clock for receiving the SMB of the next grayscale data, transmits MSB-1
of SID. If output voltage is 0.3 V (typical) when the output sink current turns on, LOD status flage becomes
active. The LOD status flag is an internal signal that pulls XERR pin down to low when the LOD status flag
becomes active. The delay time, tpd2 (1 ms maximum), is from the time of turning on the output sink current to
the time LOD status flage becomes valid. The timing for each channel's LOD status to become valid is shifted by
the 30-ns (maximum) channel-to-channel turn-on time. After the first GSCLK goes high, OUT0 LOD status is
valid; tpd3 + tpd2 = 60 ns + 1 ms. OUT1 LOD status is valid; tpd3 + td + tpd2 = 60 ns + 30 ns + 1 ms = 1.09 ms.
OUT2 LOD status is valid; tpd3 + 2*td + tpd2 = 1.12 ms, and so on. It takes 1.51 ms maximum (tpd3 + 15*td +
tpd2) from the first GSCLK rising edge until all LOD become valid; tsuLOD must be 1.51 ms (see Figure 21) to
ensure that all LOD data are valid.
Figure 20. Status Information Data Packet Format

VPRG
XLAT
SIN
SCLK
SOUT
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
1 192 193 1 192
1 4096
GS1
MSB
GS1
LSB
GS1
MSB
GS2
MSB
GS2
LSB
GS2
MSB
SID1
MSB
SID1
MSB-1
SID1
LSB
- -
tpd3
tpd3 + 15 x td + tpd2
td
15 x td
tpd2
GS Data Input Mode
1st GS Data Input Cycle 2nd GS Data Input Cycle
(1st GS Data Output Cycle)
tsuLOD
tpd4 + 15 x td + tpd3
TLC5940-EP
Figure 21. Readout Status Information Data (SID) Timing Chart
GRAYSCALE PWM OPERATION
The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low
increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following
rising edge of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of
each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values
are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and
completes the grayscale PWM cycle (see Figure 22). When the counter reaches a count of FFFh, the counter
stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets
the counter to zero.

TLC5940-EP
BLANK
GSCLK
GS PWM
Cycle n
GS PWM
Cycle n+1
th4 twh3
1 2 3 1
OUT0
OUT1
OUT15
XERR
n x t d
tpd1
tpd1 + td
tpd1 + 15 x td
tpd2
tpd3
twh1
twl1
twl1
tpd3
4096
tpd3+ n x td
tsu4
(Current)
(Current)
(Current)
Figure 22. Grayscale PWM Cycle Timing Chart
SERIAL DATA TRANSFER RATE
Figure 23 shows a cascading connection of n TLC5940 devices connected to a controller, building a basic
module of an LED display system. The maximum number of cascading TLC5940 devices depends on the
application system and is in the range of 40 devices. Equation 10 calculates the minimum frequency needed:
f(GSCLK) 4096 f(update)
f(SCLK) 193 f(update) n
(10)
where:
f(GSCLK): minimum frequency needed for GSCLK
f(SCLK): minimum frequency needed for SCLK and SIN
f(update): update rate of whole cascading system
n: number cascaded of TLC5940 device

APPLICATION EXAMPLE
OUT0 OUT15
SIN SOUT
TLC5940
SCLK
XLAT
GSCLK
BLANK
VPRG
IREF
XERR
DCPRG
TLC5940-EP
OUT0 OUT15
SIN SOUT
TLC5940
SCLK
XLAT
GSCLK
BLANK
VPRG
IREF
XERR
DCPRG
IC 0 IC n
7
SIN
XERR
SCLK
XLAT
GSCLK
Controller DCPRG
BLANK
SOUT
W_EEPROM
VPRG_D
VPRG_OE
100 k
50 k
50 k
50 k
50 k
50 k
50 k
VPRG
100 nF
VCC V(LED) V(LED) V(LED) V(LED)
100 nF
V(22V) V(22V)
VCC VCC
Figure 23. Cascading Devices

PACKAGE OPTION ADDENDUM
www.ti.com 31-May-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLC5940QPWPREP ACTIVE HTSSOP PWP 28 2000 Green (RoHS
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TLC5940EP
TLC5940QRHBREP ACTIVE VQFN RHB 32 3000 Green (RoHS
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TLC
5940EP
V62/10610-01XE ACTIVE HTSSOP PWP 28 2000 Green (RoHS
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TLC5940EP
V62/10610-01YE ACTIVE VQFN RHB 32 3000 Green (RoHS
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TLC
5940EP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a ~ will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM
www.ti.com 31-May-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF TLC5940-EP :
• Catalog: TLC5940
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

www.ti.com 27-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
PACKAGE MATERIALS INFORMATION
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TLC5940QRHBREP VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
Pack Materials-Page 1

www.ti.com 27-Jul-2013
*All dimensions are nominal
PACKAGE MATERIALS INFORMATION
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC5940QRHBREP VQFN RHB 32 3000 367.0 367.0 35.0
Pack Materials-Page 2

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