TMS20DM8148 Embedded Linux Session II

TMS20DM8148 Embedded Linux Session II

• 1.
  Embedded Linux - TMS320DM8148Hardware Session II
• 2.
  Hardware Overview • DavinciVideo Processor • Highly Integrated, programmable platforms • Target applications like – HD Video Conferencing – Skype Endpoints – Video Surveillance DVRs – IP Netcams – Digital Signage Media Players – Mobile Medical Imaging – Network Projectors – Home Audio & Video Equipments
• 3.
  Hardware Architecture
• 4.
  Processor – Overview •High Performance Davinci Video Processors – Up-to 1GHz ARM Cortex-A8 Core – Up-to 750MHz C674x VLIW DSP – Up-to 6000MIPS and 450 MFLOPS – Fully software compatible with C67x & C64x
• 5.
  ARM Cortex-A8 Core •ARMv7 Architecture – Superscalar Processor Core – Neon Multimedia Architecture – Supports Integer & Floating point – Jazelle RCT Execution Environment • ARM Cortex-A8 Memory Architecture – 32KB of Instruction & Data Caches – 512KB of L2 Cache – 64KB of RAM, 48KB of Boot ROM
• 6.
  VLIW DSP • 64Bit General Purpose Registers • Six Arithmetic Logic Units • Two Multiply Functional Units – IEEE Floating Point Multiply – Fixed point Multiply Support • Memory Architecture – 32KB of L1P RAM / Cache – 32KB of L1D RAM / Cache – 256KB of L2 Unified Mapped RAM
• 7.
  Internal Memory • SystemMemory Management Unit • 128 KB of On Chip Memory Controller (OCMC) RAM.
• 8.
  Imaging Sub System •Imaging Subsystem ( ISS ) – Camera Sensor Connection • Parallel Camera Connection for RAW ( Upto 16Bit) • BT.656 & BT.1120 ( 8 and 16 Bit ) – Image Sensor Interface ( ISIF ) • Handles Image & Video Data from Sensor – Resizer • Resizing the image from 1/16x to 8x • Able to generates Two Different Resizing Outputs concurrently
• 9.
  HDVICP v2 • HighDefinition Video Image Co Processing – Encode, Decode, Transcode operations – H.264 – MPEG-2 – VC-1 – MPEG-4 – SP/ASP – JPEG / MJPEG
• 10.
  Media Controller • Controlsthe blocks – HDVPSS – HDVICP2 – ISS
• 11.
  SGX 3D GraphicsEngine • Graphics Engine – Delivers up to 25 Mpoly / sec – Universal Scalable Shader Engine – Direct 3D Mobile – OpenGL ES 1.1 and 2.0 – OpenVG 1.0 – OpenMax – Advanced Geometry DMA Driven – Programmable HQ Image Anti-Aliasing
• 12.
  Video Capture • Two165MHz, 2-Channel HD Video Capture Modules – One 16/24 bit HD Input or Dual 8 Bit SD Input Channels – One 8/16/24 Bit input and one 8 Bit only Input Channels
• 13.
  Video Display Outputs •Two 165-MHz HD Video Display Outputs – One 16, 24, 30 Bit Output and One 16 or 24 Bit Output – Composite or S-Video Analog Output – Macrovision Support Available – Digital HDMI 1.3 Transmitter with integrated PHY – Advanced Video Processing Features • Scan Conversion • Format Conversion • Rate Conversion – Three Graphics Layers & Compositors
• 14.
  DDR2/DDR3 SDRAM • Supportsup to DDR2-800 and DDR3-1066 • Supports up to 8 Devices • Total Addressable Space – 2GB • Dynamic Memory Mapping – Programmable Multi-Zone Memory mapping & interleaving – Enables Efficient 2D Block Addresses – Optimized Interleaved Access
• 15.
  GPMC • General PurposeMemory Controller – 8 or 16 Multiplexed Address and Data Bus – 512MB of Address Space divided among 8 chip selects – Direct interface to NOR, NAND Flash, SRAM, Pseudo-RAM – Error Location Modules – Flexible Asynchronous Protocol for interface to FPGA, CPLD, ASIC and so forth.
• 16.
  Peripherals • Dual Port10/100/1000 Ethernet – IEEE 802.3 Complaint – MII/RMII/GMII/RGMII Media Independent Interfaces – Management Data IO Module – Reset Isolation – IEEE 1588 Time Stamping and Industrial Ethernet Protocols • Dual USB 2.0 with Integrated PHY – USB 2.0 High & Full Speed Clients – USB 2.0 High, Full & Low Speed Hosts & USB OTGs
• 17.
  Peripherals • One PCIExpress 2.0 port – With Integrated PHY – Single Port with One Lane at 5.o GT/s – Configurable as Root Complex & Endpoint • Eight 32 Bit General Purpose Timer • One System Watch Dog Timer • Six Configurable UARTs – UART0 with modem controls – Supports up to 3.6864 Mbps UART0/1/2 – Supports up to 12 Mbps UART3/4/5 – SIR, MIR, FIR ( 4.0 MBAUD )
• 18.
  Peripherals • Four SerialPeripheral Interfaces – Each with four Chip Selects • Three MMC/SD/SDIO Interfaces – Supports upto 1 / 4 / 8 bit modes • Dual Controller Area Network Modules – CAN Version 2 Part A, B • Four Integrated Circuits ( I2C ) Ports • Six Multi Channel Audio Serial Ports • Multi Channel Buffered Serial Ports
• 19.
  Peripherals • Serial ATA –3.0 Gbps with Integrated PHY – Hardware Assisted Native Command Queuing from up to 32 Entries – Supports Port Multiplier and Command based switching • Real Time Clock – One Time for Periodic Interrupt Generation • Up to 128 General Purpose IO (GPIO) pins • One spin lock module with up to 128 Hardware semaphores
• 20.
  Peripherals • Mailbox Modulewith 12 Mailboxes • On Chip ARM ROM Bootloader( RBL ) • Power, Reset and Clock Management – Multiple Independent Core Power Domains – Multiple Independent Core Votage Domains – Support for Three operating for each voltage domains – Clock enable & disable control for Subsystems & peripherals
• 21.
  Peripherals • Embedded TraceBuffer – 32KB of ETB – 5 pin interface for Debug • IEEE 1149.1 JTAG Compatible • 684 pin BGA 0.8 mm Ball pitch with Via Channel • 45 nm CMOS Technology • 1.8 and 3.3 Volts Dual Voltage buffers for General IOs