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Presented by : Silicon Mentor
www.siliconmentor.com
Applications of Ultra Low
Power Technique On FULL
Adder
Outline
 INRODUCTION
 SOLUTIONS
 FULL ADDER
 USES OF FULL ADDER
 ULTRA LOW POWER DESIGN OF FULL ADDER
 DIAGRAM OF ULPFA
 ADVANTAGES
 8-BIT RIPPLE-CARRY ADDER
 CONCLUSION
INTRODUCTION
• Recently, building low-power VLSI systems has emerged
as highly in demand because of the fast growing
technologies in mobile communication and computation.
• The battery technology doesn’t advance at the same rate
as the microelectronics technology.
• There is a limited amount of power Available for the
mobile systems.
• We are faced with more constraints: high speed, high
throughput, small silicon area, and at the same time,
low-power consumption.
HOW WE CAN REDUCE THIS?
• Building low-power, high-performance adder cells is of great
interest.
• By suitable power management, particularly as systems spend
most of their time in standby mode.
• By design low-power (LP) circuits. This choice closely depends
on the design style used.
• Full adders have been investigated by the academic and
industrial research communities. The usual performance
evaluations are speed, power consumption, and area.
FULL ADDER
• A Full Adder is a combinational digital circuit that
performs basic addition of binary inputs;
• Full adder operation provides with Sum (S) and
Carry-over (Cout) output;
USES OF FULL ADDER
• Basic building block of on-chip libraries.
• Configured according to desired complexity of arithmetic
and numeric computations.
• In processors and other kinds of computing devices,
adders are used in the arithmetic logic unit.
• Adders also use in other parts of the processor, where
they are used to calculate addresses, table indices, and
similar operations.
ULTRA LOW POWER FULL ADDER
• The logic styles used to implement the hybrid adder:
 BBL-logic(Branch-Based logic):for carry block.
 PT-Logic(Pass Transistor): for sum block
• Implementation of sum block using BBL requires 24
transistors, which is not advantageous.So the sum block has
been implemented using pass transistor logic.
BLOCK DIAGRAM
 PASS TRANSISTOR :  BRANCH BASED LOGIC:
ADVANTAGES OF ULPFA
• implementation of the full-adder with the BBL-PT logic style
only 23 transistors are used.
• But in CMOS full adder 28-transistor and in CPL full adder 32-
transistor are used.
• So BBL-PT full adder is more advantageous.
Ripple Carry Adder(RCA) Using Full
Adder As Basic Cell
• A standard 8-bit Ripple-Carry Adder(RCA) built as a cascade
from eight 1-bit full-adders
Circuit Description
• Each full adder inputs a Cin, which is the Cout of the previous
adder. This kind of adder is a Ripple Carry Adder.
• Each carry bit "ripples" to the next full adder.
• Each stage of the adder has to wait until the previous stage
has calculated and propagates its carry output signal.
CONCLUSION
• The power consumption is decrease due to the reduction of
transistors.
• The total layout area also reduce.
• The packing density is increase because of the less number of
transistor.
• The speed and performance of the cell is also increase.
• The 8-bit RCA circuit based on the ULPFA achieves both total
and leakage power reductions of more than 50% compared to
the 8-bit RCA circuit implemented with a conventional static
CMOS full adder.
Contact Us for M.tech/PhD Research Project Guidance
Phone : 08130809758
Email: info@siliconmentor.com
THANK YOU

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Vlsi ieee projects

  • 1. Presented by : Silicon Mentor www.siliconmentor.com Applications of Ultra Low Power Technique On FULL Adder
  • 2. Outline  INRODUCTION  SOLUTIONS  FULL ADDER  USES OF FULL ADDER  ULTRA LOW POWER DESIGN OF FULL ADDER  DIAGRAM OF ULPFA  ADVANTAGES  8-BIT RIPPLE-CARRY ADDER  CONCLUSION
  • 3. INTRODUCTION • Recently, building low-power VLSI systems has emerged as highly in demand because of the fast growing technologies in mobile communication and computation. • The battery technology doesn’t advance at the same rate as the microelectronics technology. • There is a limited amount of power Available for the mobile systems. • We are faced with more constraints: high speed, high throughput, small silicon area, and at the same time, low-power consumption.
  • 4. HOW WE CAN REDUCE THIS? • Building low-power, high-performance adder cells is of great interest. • By suitable power management, particularly as systems spend most of their time in standby mode. • By design low-power (LP) circuits. This choice closely depends on the design style used. • Full adders have been investigated by the academic and industrial research communities. The usual performance evaluations are speed, power consumption, and area.
  • 5. FULL ADDER • A Full Adder is a combinational digital circuit that performs basic addition of binary inputs; • Full adder operation provides with Sum (S) and Carry-over (Cout) output;
  • 6. USES OF FULL ADDER • Basic building block of on-chip libraries. • Configured according to desired complexity of arithmetic and numeric computations. • In processors and other kinds of computing devices, adders are used in the arithmetic logic unit. • Adders also use in other parts of the processor, where they are used to calculate addresses, table indices, and similar operations.
  • 7. ULTRA LOW POWER FULL ADDER • The logic styles used to implement the hybrid adder:  BBL-logic(Branch-Based logic):for carry block.  PT-Logic(Pass Transistor): for sum block • Implementation of sum block using BBL requires 24 transistors, which is not advantageous.So the sum block has been implemented using pass transistor logic.
  • 8. BLOCK DIAGRAM  PASS TRANSISTOR :  BRANCH BASED LOGIC:
  • 9. ADVANTAGES OF ULPFA • implementation of the full-adder with the BBL-PT logic style only 23 transistors are used. • But in CMOS full adder 28-transistor and in CPL full adder 32- transistor are used. • So BBL-PT full adder is more advantageous.
  • 10. Ripple Carry Adder(RCA) Using Full Adder As Basic Cell • A standard 8-bit Ripple-Carry Adder(RCA) built as a cascade from eight 1-bit full-adders
  • 11. Circuit Description • Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a Ripple Carry Adder. • Each carry bit "ripples" to the next full adder. • Each stage of the adder has to wait until the previous stage has calculated and propagates its carry output signal.
  • 12. CONCLUSION • The power consumption is decrease due to the reduction of transistors. • The total layout area also reduce. • The packing density is increase because of the less number of transistor. • The speed and performance of the cell is also increase. • The 8-bit RCA circuit based on the ULPFA achieves both total and leakage power reductions of more than 50% compared to the 8-bit RCA circuit implemented with a conventional static CMOS full adder.
  • 13. Contact Us for M.tech/PhD Research Project Guidance Phone : 08130809758 Email: [email protected] THANK YOU