Remove HP/Intel Itanium support.

This CPU architecture has been discontinued.  We already removed HP-UX
support, we never supported Windows/Itanium, and the open source
operating systems that a vintage hardware owner might hope to run have
all either ended Itanium support or never fully released support (NetBSD
may eventually).  The extra code we carry for this rare ISA is now
untested.  It seems like a good time to remove it.

Reviewed-by: Tom Lane <[email protected]>
Reviewed-by: Andres Freund <[email protected]>
Discussion: https://postgr.es/m/1415825.1656893299%40sss.pgh.pa.us

5 files changed, 1 insertions, 103 deletions

diff --git a/src/include/miscadmin.h b/src/include/miscadmin.h
index 0af130fbc5d..ea9a56d3955 100644
--- a/src/include/miscadmin.h
+++ b/src/include/miscadmin.h
@@ -279,15 +279,7 @@ extern PGDLLIMPORT bool VacuumCostActive;
 
 /* in tcop/postgres.c */
 
-#if defined(__ia64__) || defined(__ia64)
-typedef struct
-{
-	char	   *stack_base_ptr;
-	char	   *register_stack_base_ptr;
-} pg_stack_base_t;
-#else
 typedef char *pg_stack_base_t;
-#endif
 
 extern pg_stack_base_t set_stack_base(void);
 extern void restore_stack_base(pg_stack_base_t base);
diff --git a/src/include/port/atomics.h b/src/include/port/atomics.h
index 33b7fd6042c..f7cd0f6f20c 100644
--- a/src/include/port/atomics.h
+++ b/src/include/port/atomics.h
@@ -68,8 +68,6 @@
 #include "port/atomics/arch-arm.h"
 #elif defined(__i386__) || defined(__i386) || defined(__x86_64__)
 #include "port/atomics/arch-x86.h"
-#elif defined(__ia64__) || defined(__ia64)
-#include "port/atomics/arch-ia64.h"
 #elif defined(__ppc__) || defined(__powerpc__) || defined(__ppc64__) || defined(__powerpc64__)
 #include "port/atomics/arch-ppc.h"
 #elif defined(__hppa) || defined(__hppa__)
diff --git a/src/include/port/atomics/arch-ia64.h b/src/include/port/atomics/arch-ia64.h
deleted file mode 100644
index 264d2316b97..00000000000
--- a/src/include/port/atomics/arch-ia64.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*-------------------------------------------------------------------------
- *
- * arch-ia64.h
- *	  Atomic operations considerations specific to intel itanium
- *
- * Portions Copyright (c) 1996-2022, PostgreSQL Global Development Group
- * Portions Copyright (c) 1994, Regents of the University of California
- *
- * NOTES:
- *
- * src/include/port/atomics/arch-ia64.h
- *
- *-------------------------------------------------------------------------
- */
-
-/*
- * Itanium is weakly ordered, so read and write barriers require a full
- * fence.
- */
-#if defined(__INTEL_COMPILER)
-#	define pg_memory_barrier_impl()		__mf()
-#elif defined(__GNUC__)
-#	define pg_memory_barrier_impl()		__asm__ __volatile__ ("mf" : : : "memory")
-#endif
-
-/* per architecture manual doubleword accesses have single copy atomicity */
-#define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY
diff --git a/src/include/port/atomics/generic-msvc.h b/src/include/port/atomics/generic-msvc.h
index 6294162b4cc..1a4adfde686 100644
--- a/src/include/port/atomics/generic-msvc.h
+++ b/src/include/port/atomics/generic-msvc.h
@@ -86,7 +86,7 @@ pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
 	return ret;
 }
 
-/* Only implemented on itanium and 64bit builds */
+/* Only implemented on 64bit builds */
 #ifdef _WIN64
 #pragma intrinsic(_InterlockedExchangeAdd64)
 
diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
index 1e1eb324b43..c4a19b2f433 100644
--- a/src/include/storage/s_lock.h
+++ b/src/include/storage/s_lock.h
@@ -250,71 +250,6 @@ spin_delay(void)
 #endif	 /* __x86_64__ */
 
 
-#if defined(__ia64__) || defined(__ia64)
-/*
- * Intel Itanium, gcc or Intel's compiler.
- *
- * Itanium has weak memory ordering, but we rely on the compiler to enforce
- * strict ordering of accesses to volatile data.  In particular, while the
- * xchg instruction implicitly acts as a memory barrier with 'acquire'
- * semantics, we do not have an explicit memory fence instruction in the
- * S_UNLOCK macro.  We use a regular assignment to clear the spinlock, and
- * trust that the compiler marks the generated store instruction with the
- * ".rel" opcode.
- *
- * Testing shows that assumption to hold on gcc, although I could not find
- * any explicit statement on that in the gcc manual.  In Intel's compiler,
- * the -m[no-]serialize-volatile option controls that, and testing shows that
- * it is enabled by default.
- *
- * While icc accepts gcc asm blocks on x86[_64], this is not true on ia64
- * (at least not in icc versions before 12.x).  So we have to carry a separate
- * compiler-intrinsic-based implementation for it.
- */
-#define HAS_TEST_AND_SET
-
-typedef unsigned int slock_t;
-
-#define TAS(lock) tas(lock)
-
-/* On IA64, it's a win to use a non-locking test before the xchg proper */
-#define TAS_SPIN(lock)	(*(lock) ? 1 : TAS(lock))
-
-#ifndef __INTEL_COMPILER
-
-static __inline__ int
-tas(volatile slock_t *lock)
-{
-	long int	ret;
-
-	__asm__ __volatile__(
-		"	xchg4 	%0=%1,%2	\n"
-:		"=r"(ret), "+m"(*lock)
-:		"r"(1)
-:		"memory");
-	return (int) ret;
-}
-
-#else /* __INTEL_COMPILER */
-
-static __inline__ int
-tas(volatile slock_t *lock)
-{
-	int		ret;
-
-	ret = _InterlockedExchange(lock,1);	/* this is a xchg asm macro */
-
-	return ret;
-}
-
-/* icc can't use the regular gcc S_UNLOCK() macro either in this case */
-#define S_UNLOCK(lock)	\
-	do { __memory_barrier(); *(lock) = 0; } while (0)
-
-#endif /* __INTEL_COMPILER */
-#endif	 /* __ia64__ || __ia64 */
-
-
 /*
  * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
  *