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Help regarding axi register configuration

Status: Open.

#89 In alexforencich/verilog-axi;

· vinayaka1 opened on Apr 3, 2025

DMA: how do I know if DMA has finished (documentation)?

Status: Open.

#88 In alexforencich/verilog-axi;

· Vincer239 opened on Dec 5, 2024

The range of m_select_reg becomes ascending

Status: Open.

#86 In alexforencich/verilog-axi;

· offnaria opened on Dec 5, 2024

Crossbar locks up after reading to write-only address

Status: Open.

#84 In alexforencich/verilog-axi;

· aharrysrc opened on Dec 3, 2024

it seem like axi_adapter not support outstanding transfer

Status: Open.

#83 In alexforencich/verilog-axi;

· DV-Carium opened on Sep 23, 2024

axil_fifo

Status: Open.

#82 In alexforencich/verilog-axi;

· 0TulipRose0 opened on Aug 23, 2024

<code>axi_dma_wr</code> does not respect TKEEP

Status: Open.

#81 In alexforencich/verilog-axi;

· KireinaHoro opened on Aug 22, 2024

axi_dma_wr seems to give done status before fully writing to DDR?

Status: Open.

#80 In alexforencich/verilog-axi;

· abarajithan11 opened on Jul 16, 2024

Parameters not passed on to axi_crossbar_wr and axi_crossbar_rd in axi_crossbar.v

Status: Open.

#79 In alexforencich/verilog-axi;

· RiceShelley opened on Jul 1, 2024

Q: DMA, desc_len VS tlast in axi_dma_wr

Status: Open.

#78 In alexforencich/verilog-axi;

· abarajithan11 opened on May 9, 2024

about AXI DMA

Status: Open.

#76 In alexforencich/verilog-axi;

· zengzhengqi0524 opened on May 8, 2024

About AXI_FULL_CDC

Status: Open.

#74 In alexforencich/verilog-axi;

· LZR1567 opened on Mar 30, 2024