Add a lexer for RISC-V assembly #2145
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Author
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One thing I wasn't quite sure about - there's Also more testing & suggestions very welcome! |
jneen
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Jul 26, 2025
added 2 commits
July 28, 2025 11:00
This adds a basic lexer for RISC-V assembly. Like all assembly (as far as I know) there isn't really a formal grammar, and compilers just kind of do whatever, so this is a best effort. There may be valid assembly it does not highlight properly. I have tested it on several random samples from the internet and it seems to be ok though. The included demo is from the RISC-V ISA manual: https://riscv-specs.timhutt.co.uk/spec/20240411/unpriv-isa-asciidoc.html#_sgemm_example
Sets are the preferred method. I also reorganised the states a bit to make things work slightly more nicely (e.g. it highlights registers in preprocessor definitions).
Author
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@tancnle any chance you could review this? |
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This adds a basic lexer for RISC-V assembly. Like all assembly (as far as I know) there isn't really a formal grammar, and compilers just kind of do whatever, so this is a best effort. There may be valid assembly it does not highlight properly.
I have tested it on several random samples from the internet and it seems to be ok though.
The included demo is from the RISC-V ISA manual: https://riscv-specs.timhutt.co.uk/spec/20240411/unpriv-isa-asciidoc.html#_sgemm_example