LLVM 20.0.0git
RISCVDisassembler.cpp
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1//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVMCTargetDesc.h"
15#include "TargetInfo/RISCVTargetInfo.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Endian.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "riscv-disassembler"
29
30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
32namespace {
33class RISCVDisassembler : public MCDisassembler {
34 std::unique_ptr<MCInstrInfo const> const MCII;
35
36public:
37 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
38 MCInstrInfo const *MCII)
39 : MCDisassembler(STI, Ctx), MCII(MCII) {}
40
41 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
42 ArrayRef<uint8_t> Bytes, uint64_t Address,
43 raw_ostream &CStream) const override;
44
45private:
46 void addSPOperands(MCInst &MI) const;
47
48 DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
49 ArrayRef<uint8_t> Bytes, uint64_t Address,
50 raw_ostream &CStream) const;
51
52 DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
53 ArrayRef<uint8_t> Bytes, uint64_t Address,
54 raw_ostream &CStream) const;
55 DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
56 ArrayRef<uint8_t> Bytes, uint64_t Address,
57 raw_ostream &CStream) const;
58};
59} // end anonymous namespace
60
61static MCDisassembler *createRISCVDisassembler(const Target &T,
62 const MCSubtargetInfo &STI,
63 MCContext &Ctx) {
64 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
65}
66
67extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
68 // Register the disassembler for each target.
69 TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
70 createRISCVDisassembler);
71 TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
72 createRISCVDisassembler);
73}
74
75static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
76 uint64_t Address,
77 const MCDisassembler *Decoder) {
78 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
79
80 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
81 return MCDisassembler::Fail;
82
83 MCRegister Reg = RISCV::X0 + RegNo;
84 Inst.addOperand(MCOperand::createReg(Reg));
85 return MCDisassembler::Success;
86}
87
88static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo,
89 uint64_t Address,
90 const MCDisassembler *Decoder) {
91 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
92
93 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
94 return MCDisassembler::Fail;
95
96 MCRegister Reg = RISCV::X0_H + RegNo;
97 Inst.addOperand(MCOperand::createReg(Reg));
98 return MCDisassembler::Success;
99}
100
101static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo,
102 uint64_t Address,
103 const MCDisassembler *Decoder) {
104 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
105
106 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
107 return MCDisassembler::Fail;
108
109 MCRegister Reg = RISCV::X0_W + RegNo;
110 Inst.addOperand(MCOperand::createReg(Reg));
111 return MCDisassembler::Success;
112}
113
114static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
115 uint64_t Address,
116 const MCDisassembler *Decoder) {
117 MCRegister Reg = RISCV::X0 + RegNo;
118 if (Reg != RISCV::X1 && Reg != RISCV::X5)
119 return MCDisassembler::Fail;
120
121 Inst.addOperand(MCOperand::createReg(Reg));
122 return MCDisassembler::Success;
123}
124
125static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
126 uint64_t Address,
127 const MCDisassembler *Decoder) {
128 if (RegNo >= 32)
129 return MCDisassembler::Fail;
130
131 MCRegister Reg = RISCV::F0_H + RegNo;
132 Inst.addOperand(MCOperand::createReg(Reg));
133 return MCDisassembler::Success;
134}
135
136static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
137 uint64_t Address,
138 const MCDisassembler *Decoder) {
139 if (RegNo >= 32)
140 return MCDisassembler::Fail;
141
142 MCRegister Reg = RISCV::F0_F + RegNo;
143 Inst.addOperand(MCOperand::createReg(Reg));
144 return MCDisassembler::Success;
145}
146
147static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
148 uint64_t Address,
149 const MCDisassembler *Decoder) {
150 if (RegNo >= 8) {
151 return MCDisassembler::Fail;
152 }
153 MCRegister Reg = RISCV::F8_F + RegNo;
154 Inst.addOperand(MCOperand::createReg(Reg));
155 return MCDisassembler::Success;
156}
157
158static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
159 uint64_t Address,
160 const MCDisassembler *Decoder) {
161 if (RegNo >= 32)
162 return MCDisassembler::Fail;
163
164 MCRegister Reg = RISCV::F0_D + RegNo;
165 Inst.addOperand(MCOperand::createReg(Reg));
166 return MCDisassembler::Success;
167}
168
169static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
170 uint64_t Address,
171 const MCDisassembler *Decoder) {
172 if (RegNo >= 8) {
173 return MCDisassembler::Fail;
174 }
175 MCRegister Reg = RISCV::F8_D + RegNo;
176 Inst.addOperand(MCOperand::createReg(Reg));
177 return MCDisassembler::Success;
178}
179
180static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
181 uint64_t Address,
182 const MCDisassembler *Decoder) {
183 if (RegNo == 0) {
184 return MCDisassembler::Fail;
185 }
186
187 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
188}
189
190static DecodeStatus
191DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
192 const MCDisassembler *Decoder) {
193 if (RegNo == 2) {
194 return MCDisassembler::Fail;
195 }
196
197 return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
198}
199
200static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
201 uint64_t Address,
202 const MCDisassembler *Decoder) {
203 if (RegNo >= 8)
204 return MCDisassembler::Fail;
205
206 MCRegister Reg = RISCV::X8 + RegNo;
207 Inst.addOperand(MCOperand::createReg(Reg));
208 return MCDisassembler::Success;
209}
210
211static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
212 uint64_t Address,
213 const MCDisassembler *Decoder) {
214 if (RegNo >= 32 || RegNo % 2)
215 return MCDisassembler::Fail;
216
217 const RISCVDisassembler *Dis =
218 static_cast<const RISCVDisassembler *>(Decoder);
219 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
220 MCRegister Reg = RI->getMatchingSuperReg(
221 RISCV::X0 + RegNo, RISCV::sub_gpr_even,
222 &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
223 Inst.addOperand(MCOperand::createReg(Reg));
224 return MCDisassembler::Success;
225}
226
227static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo,
228 uint64_t Address,
229 const void *Decoder) {
230 if (RegNo >= 8)
231 return MCDisassembler::Fail;
232
233 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
234 Inst.addOperand(MCOperand::createReg(Reg));
235 return MCDisassembler::Success;
236}
237
238static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
239 uint64_t Address,
240 const MCDisassembler *Decoder) {
241 if (RegNo >= 32)
242 return MCDisassembler::Fail;
243
244 MCRegister Reg = RISCV::V0 + RegNo;
245 Inst.addOperand(MCOperand::createReg(Reg));
246 return MCDisassembler::Success;
247}
248
249static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
250 uint64_t Address,
251 const MCDisassembler *Decoder) {
252 if (RegNo >= 32 || RegNo % 2)
253 return MCDisassembler::Fail;
254
255 const RISCVDisassembler *Dis =
256 static_cast<const RISCVDisassembler *>(Decoder);
257 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
258 MCRegister Reg =
259 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
260 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
261
262 Inst.addOperand(MCOperand::createReg(Reg));
263 return MCDisassembler::Success;
264}
265
266static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
267 uint64_t Address,
268 const MCDisassembler *Decoder) {
269 if (RegNo >= 32 || RegNo % 4)
270 return MCDisassembler::Fail;
271
272 const RISCVDisassembler *Dis =
273 static_cast<const RISCVDisassembler *>(Decoder);
274 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
275 MCRegister Reg =
276 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
277 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
278
279 Inst.addOperand(MCOperand::createReg(Reg));
280 return MCDisassembler::Success;
281}
282
283static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
284 uint64_t Address,
285 const MCDisassembler *Decoder) {
286 if (RegNo >= 32 || RegNo % 8)
287 return MCDisassembler::Fail;
288
289 const RISCVDisassembler *Dis =
290 static_cast<const RISCVDisassembler *>(Decoder);
291 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
292 MCRegister Reg =
293 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
294 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
295
296 Inst.addOperand(MCOperand::createReg(Reg));
297 return MCDisassembler::Success;
298}
299
300static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
301 uint64_t Address,
302 const MCDisassembler *Decoder) {
303 if (RegNo)
304 return MCDisassembler::Fail;
305
306 Inst.addOperand(MCOperand::createReg(RISCV::V0));
307 return MCDisassembler::Success;
308}
309
310static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
311 uint64_t Address,
312 const MCDisassembler *Decoder) {
313 if (RegNo >= 2)
314 return MCDisassembler::Fail;
315
316 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
317
318 Inst.addOperand(MCOperand::createReg(Reg));
319 return MCDisassembler::Success;
320}
321
322template <unsigned N>
323static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
324 int64_t Address,
325 const MCDisassembler *Decoder) {
326 assert(isUInt<N>(Imm) && "Invalid immediate");
327 Inst.addOperand(MCOperand::createImm(Imm));
328 return MCDisassembler::Success;
329}
330
331static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
332 int64_t Address,
333 const MCDisassembler *Decoder) {
334 assert(isUInt<6>(Imm) && "Invalid immediate");
335
336 if (!Decoder->getSubtargetInfo().hasFeature(RISCV::Feature64Bit) &&
337 !isUInt<5>(Imm))
338 return MCDisassembler::Fail;
339
340 Inst.addOperand(MCOperand::createImm(Imm));
341 return MCDisassembler::Success;
342}
343
344template <unsigned N>
345static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
346 int64_t Address,
347 const MCDisassembler *Decoder) {
348 if (Imm == 0)
349 return MCDisassembler::Fail;
350 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
351}
352
353static DecodeStatus
354decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
355 const MCDisassembler *Decoder) {
356 if (Imm == 0)
357 return MCDisassembler::Fail;
358 return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
359}
360
361template <unsigned N>
362static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
363 int64_t Address,
364 const MCDisassembler *Decoder) {
365 assert(isUInt<N>(Imm) && "Invalid immediate");
366 // Sign-extend the number in the bottom N bits of Imm
367 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
368 return MCDisassembler::Success;
369}
370
371template <unsigned N>
372static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
373 int64_t Address,
374 const MCDisassembler *Decoder) {
375 if (Imm == 0)
376 return MCDisassembler::Fail;
377 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
378}
379
380template <unsigned N>
381static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm,
382 int64_t Address,
383 const MCDisassembler *Decoder) {
384 assert(isUInt<N>(Imm) && "Invalid immediate");
385 // Sign-extend the number in the bottom N bits of Imm after accounting for
386 // the fact that the N bit immediate is stored in N-1 bits (the LSB is
387 // always zero)
388 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
389 return MCDisassembler::Success;
390}
391
392static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
393 int64_t Address,
394 const MCDisassembler *Decoder) {
395 assert(isUInt<6>(Imm) && "Invalid immediate");
396 if (Imm > 31) {
397 Imm = (SignExtend64<6>(Imm) & 0xfffff);
398 }
399 Inst.addOperand(MCOperand::createImm(Imm));
400 return MCDisassembler::Success;
401}
402
403static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
404 const MCDisassembler *Decoder) {
405 assert(isUInt<3>(Imm) && "Invalid immediate");
406 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
407 return MCDisassembler::Fail;
408
409 Inst.addOperand(MCOperand::createImm(Imm));
410 return MCDisassembler::Success;
411}
412
413static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
414 const MCDisassembler *Decoder) {
415 assert(isUInt<3>(Imm) && "Invalid immediate");
416 if (Imm != RISCVFPRndMode::RTZ)
417 return MCDisassembler::Fail;
418
419 Inst.addOperand(MCOperand::createImm(Imm));
420 return MCDisassembler::Success;
421}
422
423static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
424 uint64_t Address,
425 const MCDisassembler *Decoder);
426
427static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
428 uint64_t Address,
429 const MCDisassembler *Decoder);
430
431static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
432 uint64_t Address,
433 const MCDisassembler *Decoder);
434
435static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
436 uint64_t Address,
437 const MCDisassembler *Decoder);
438
439static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
440 uint64_t Address,
441 const MCDisassembler *Decoder);
442
443static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
444 uint64_t Address,
445 const MCDisassembler *Decoder);
446
447static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
448 uint64_t Address, const void *Decoder);
449
450static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
451 const MCDisassembler *Decoder);
452
453static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
454 uint64_t Address, const void *Decoder);
455
456static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
457 uint64_t Address,
458 const MCDisassembler *Decoder);
459
460#include "RISCVGenDisassemblerTables.inc"
461
462static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
463 uint64_t Address,
464 const MCDisassembler *Decoder) {
465 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
466 [[maybe_unused]] DecodeStatus Result =
467 DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
468 assert(Result == MCDisassembler::Success && "Invalid register");
469 Inst.addOperand(Inst.getOperand(0));
470 Inst.addOperand(MCOperand::createImm(0));
471 return MCDisassembler::Success;
472}
473
474static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
475 uint64_t Address,
476 const MCDisassembler *Decoder) {
477 uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
478 [[maybe_unused]] DecodeStatus Result =
479 DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
480 assert(Result == MCDisassembler::Success && "Invalid register");
481 return MCDisassembler::Success;
482}
483
484static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
485 uint64_t Address,
486 const MCDisassembler *Decoder) {
487 Inst.addOperand(MCOperand::createReg(RISCV::X0));
488 uint32_t SImm6 =
489 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
490 [[maybe_unused]] DecodeStatus Result =
491 decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
492 assert(Result == MCDisassembler::Success && "Invalid immediate");
493 return MCDisassembler::Success;
494}
495
496static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
497 uint64_t Address,
498 const MCDisassembler *Decoder) {
499 Inst.addOperand(MCOperand::createReg(RISCV::X0));
500 Inst.addOperand(Inst.getOperand(0));
501 uint32_t UImm6 =
502 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
503 [[maybe_unused]] DecodeStatus Result =
504 decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
505 assert(Result == MCDisassembler::Success && "Invalid immediate");
506 return MCDisassembler::Success;
507}
508
509static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
510 uint64_t Address,
511 const MCDisassembler *Decoder) {
512 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
513 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
514 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
515 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
516 return MCDisassembler::Success;
517}
518
519static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
520 uint64_t Address,
521 const MCDisassembler *Decoder) {
522 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
523 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
524 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
525 Inst.addOperand(Inst.getOperand(0));
526 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
527 return MCDisassembler::Success;
528}
529
530static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
531 uint64_t Address,
532 const MCDisassembler *Decoder) {
533 uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
534 uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
535 uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
536 uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
537 DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
538 DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
539 DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
540 [[maybe_unused]] DecodeStatus Result =
541 decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
542 assert(Result == MCDisassembler::Success && "Invalid immediate");
543
544 // Disassemble the final operand which is implicit.
545 unsigned Opcode = Inst.getOpcode();
546 bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
547 Opcode == RISCV::TH_SWD);
548 if (IsWordOp)
549 Inst.addOperand(MCOperand::createImm(3));
550 else
551 Inst.addOperand(MCOperand::createImm(4));
552
553 return MCDisassembler::Success;
554}
555
556static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
557 uint64_t Address, const void *Decoder) {
558 if (Imm <= 3)
559 return MCDisassembler::Fail;
560 Inst.addOperand(MCOperand::createImm(Imm));
561 return MCDisassembler::Success;
562}
563
564static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
565 const MCDisassembler *Decoder) {
566 uint32_t Rs1 = fieldFromInstruction(Insn, 0, 5);
567 uint32_t Rs2 = fieldFromInstruction(Insn, 5, 5);
568 DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
569 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
570 return MCDisassembler::Success;
571}
572
573static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
574 uint64_t Address, const void *Decoder) {
575 Inst.addOperand(MCOperand::createImm(Imm));
576 return MCDisassembler::Success;
577}
578
579// Add implied SP operand for C.*SP compressed instructions. The SP operand
580// isn't explicitly encoded in the instruction.
581void RISCVDisassembler::addSPOperands(MCInst &MI) const {
582 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
583 for (unsigned i = 0; i < MCID.getNumOperands(); i++)
584 if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
585 MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
586}
587
588#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \
589 DESC, ADDITIONAL_OPERATION) \
590 do { \
591 if (FEATURE_CHECKS) { \
592 LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \
593 DecodeStatus Result = \
594 decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
595 if (Result != MCDisassembler::Fail) { \
596 ADDITIONAL_OPERATION; \
597 return Result; \
598 } \
599 } \
600 } while (false)
601#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC) \
602 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
603 addSPOperands(MI))
604#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC) \
605 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
606 (void)nullptr)
607#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \
608 TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC)
609
610DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
611 ArrayRef<uint8_t> Bytes,
612 uint64_t Address,
613 raw_ostream &CS) const {
614 if (Bytes.size() < 4) {
615 Size = 0;
616 return MCDisassembler::Fail;
617 }
618 Size = 4;
619
620 uint32_t Insn = support::endian::read32le(Bytes.data());
621
622 TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
623 !STI.hasFeature(RISCV::Feature64Bit),
624 DecoderTableRV32Zdinx32,
625 "RV32Zdinx table (Double in Integer and rv32)");
626 TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) &&
627 !STI.hasFeature(RISCV::Feature64Bit),
628 DecoderTableRV32Zacas32,
629 "RV32Zacas table (Compare-And-Swap and rv32)");
630 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
631 "RVZfinx table (Float in Integer)");
632 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
633 DecoderTableXVentana32, "Ventana custom opcode table");
634 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
635 "XTHeadBa custom opcode table");
636 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
637 "XTHeadBb custom opcode table");
638 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
639 "XTHeadBs custom opcode table");
640 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
641 DecoderTableXTHeadCondMov32,
642 "XTHeadCondMov custom opcode table");
643 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
644 "XTHeadCmo custom opcode table");
645 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
646 DecoderTableXTHeadFMemIdx32,
647 "XTHeadFMemIdx custom opcode table");
648 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
649 "XTHeadMac custom opcode table");
650 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
651 DecoderTableXTHeadMemIdx32,
652 "XTHeadMemIdx custom opcode table");
653 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
654 DecoderTableXTHeadMemPair32,
655 "XTHeadMemPair custom opcode table");
656 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
657 DecoderTableXTHeadSync32,
658 "XTHeadSync custom opcode table");
659 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot,
660 DecoderTableXTHeadVdot32,
661 "XTHeadVdot custom opcode table");
662 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
663 "SiFive VCIX custom opcode table");
664 TRY_TO_DECODE_FEATURE(
665 RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
666 "SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
667 TRY_TO_DECODE_FEATURE(
668 RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
669 "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
670 TRY_TO_DECODE_FEATURE(
671 RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
672 "SiFive Matrix Multiplication Instruction opcode table");
673 TRY_TO_DECODE_FEATURE(
674 RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
675 "SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
676 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
677 DecoderTableXSiFivecdiscarddlone32,
678 "SiFive sf.cdiscard.d.l1 custom opcode table");
679 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
680 DecoderTableXSiFivecflushdlone32,
681 "SiFive sf.cflush.d.l1 custom opcode table");
682 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
683 "SiFive sf.cease custom opcode table");
684 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
685 DecoderTableXCVbitmanip32,
686 "CORE-V Bit Manipulation custom opcode table");
687 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
688 "CORE-V Event load custom opcode table");
689 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
690 "CORE-V MAC custom opcode table");
691 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
692 "CORE-V MEM custom opcode table");
693 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
694 "CORE-V ALU custom opcode table");
695 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
696 "CORE-V SIMD extensions custom opcode table");
697 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
698 "CORE-V Immediate Branching custom opcode table");
699 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32,
700 "Qualcomm uC CSR custom opcode table");
701 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
702 "Qualcomm uC Scaled Load Store custom opcode table");
703 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
704 "Qualcomm uC Arithmetic custom opcode table");
705 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcics, DecoderTableXqcics32,
706 "Qualcomm uC Conditional Select custom opcode table");
707 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilsm, DecoderTableXqcilsm32,
708 "Qualcomm uC Load Store Multiple custom opcode table");
709 TRY_TO_DECODE_FEATURE(
710 RISCV::FeatureVendorXqciac, DecoderTableXqciac32,
711 "Qualcomm uC Load-Store Address Calculation custom opcode table");
712 TRY_TO_DECODE_FEATURE(
713 RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32,
714 "Qualcomm uC Conditional Load Immediate custom opcode table");
715 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicm, DecoderTableXqcicm32,
716 "Qualcomm uC Conditional Move custom opcode table");
717 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
718 "Qualcomm uC Interrupts custom opcode table");
719 TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
720
721 return MCDisassembler::Fail;
722}
723
724DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
725 ArrayRef<uint8_t> Bytes,
726 uint64_t Address,
727 raw_ostream &CS) const {
728 if (Bytes.size() < 2) {
729 Size = 0;
730 return MCDisassembler::Fail;
731 }
732 Size = 2;
733
734 uint32_t Insn = support::endian::read16le(Bytes.data());
735 TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
736 DecoderTableRISCV32Only_16,
737 "RISCV32Only_16 table (16-bit Instruction)");
738 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZicfiss, DecoderTableZicfiss16,
739 "RVZicfiss table (Shadow Stack)");
740 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16,
741 "Zcmt table (16-bit Table Jump Instructions)");
742 TRY_TO_DECODE_FEATURE(
743 RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
744 "Zcmp table (16-bit Push/Pop & Double Move Instructions)");
745 TRY_TO_DECODE_FEATURE(
746 RISCV::FeatureVendorXqciac, DecoderTableXqciac16,
747 "Qualcomm uC Load-Store Address Calculation custom 16bit opcode table");
748 TRY_TO_DECODE_FEATURE(
749 RISCV::FeatureVendorXqcicm, DecoderTableXqcicm16,
750 "Qualcomm uC Conditional Move custom 16bit opcode table");
751 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint16,
752 "Qualcomm uC Interrupts custom 16bit opcode table");
753 TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXwchc),
754 DecoderTableXwchc16,
755 "WCH QingKe XW custom opcode table");
756 TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,
757 "RISCV_C table (16-bit Instruction)");
758
759 return MCDisassembler::Fail;
760}
761
762DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
763 ArrayRef<uint8_t> Bytes,
764 uint64_t Address,
765 raw_ostream &CS) const {
766 if (Bytes.size() < 6) {
767 Size = 0;
768 return MCDisassembler::Fail;
769 }
770 Size = 6;
771
772 uint64_t Insn = 0;
773 for (size_t i = Size; i-- != 0;) {
774 Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
775 }
776 TRY_TO_DECODE_FEATURE(
777 RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
778 "Qualcomm uC Large Offset Load Store custom 48bit opcode table");
779
780 return MCDisassembler::Fail;
781}
782
783DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
784 ArrayRef<uint8_t> Bytes,
785 uint64_t Address,
786 raw_ostream &CS) const {
787 // It's a 16 bit instruction if bit 0 and 1 are not 0b11.
788 if ((Bytes[0] & 0b11) != 0b11)
789 return getInstruction16(MI, Size, Bytes, Address, CS);
790
791 // It's a 32 bit instruction if bit 1:0 are 0b11(checked above) and bits 4:2
792 // are not 0b111.
793 if ((Bytes[0] & 0b1'1100) != 0b1'1100)
794 return getInstruction32(MI, Size, Bytes, Address, CS);
795
796 // 48-bit instructions are encoded as 0bxx011111.
797 if ((Bytes[0] & 0b11'1111) == 0b01'1111) {
798 return getInstruction48(MI, Size, Bytes, Address, CS);
799 }
800
801 // 64-bit instructions are encoded as 0x0111111.
802 if ((Bytes[0] & 0b111'1111) == 0b011'1111) {
803 Size = Bytes.size() >= 8 ? 8 : 0;
804 return MCDisassembler::Fail;
805 }
806
807 // Remaining cases need to check a second byte.
808 if (Bytes.size() < 2) {
809 Size = 0;
810 return MCDisassembler::Fail;
811 }
812
813 // 80-bit through 176-bit instructions are encoded as 0bxnnnxxxx_x1111111.
814 // Where the number of bits is (80 + (nnn * 16)) for nnn != 0b111.
815 unsigned nnn = (Bytes[1] >> 4) & 0b111;
816 if (nnn != 0b111) {
817 Size = 10 + (nnn * 2);
818 if (Bytes.size() < Size)
819 Size = 0;
820 return MCDisassembler::Fail;
821 }
822
823 // Remaining encodings are reserved for > 176-bit instructions.
824 Size = 0;
825 return MCDisassembler::Fail;
826}
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:167
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:128
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:112
TRY_TO_DECODE
#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC)
Definition: RISCVDisassembler.cpp:604
decodeRegReg
static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:564
decodeZcmpRlist
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:556
decodeRVCInstrRdRs1Rs2
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:519
decodeUImmLog2XLenOperand
static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:331
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: RISCVDisassembler.cpp:30
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:362
DecodeGPRX1X5RegisterClass
static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:114
DecodeGPRCRegisterClass
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:200
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:158
decodeUImmLog2XLenNonZeroOperand
static DecodeStatus decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:354
decodeRTZArg
static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:413
createRISCVDisassembler
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: RISCVDisassembler.cpp:61
decodeRVCInstrRdRs1ImmZero
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:462
DecodeGPRF16RegisterClass
static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:88
TRY_TO_DECODE_FEATURE
#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC)
Definition: RISCVDisassembler.cpp:607
decodeSImmOperandAndLsl1
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:381
DecodeFPR32CRegisterClass
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:147
decodeXTHeadMemPair
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:530
decodeCLUIImmOperand
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:392
decodeCSSPushPopchk
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:474
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:323
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:136
DecodeVRM8RegisterClass
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:283
DecodeVRM4RegisterClass
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:266
decodeRVCInstrRdSImm
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:484
DecodeVRRegisterClass
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:238
DecodeVRM2RegisterClass
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:249
DecodeGPRPairRegisterClass
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:211
decodeZcmpSpimm
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:573
DecodeGPRNoX0X2RegisterClass
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:191
decodeRVCInstrRdRs2
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:509
decodeSImmNonZeroOperand
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:372
DecodeVMV0RegisterClass
static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:300
DecodeFPR64CRegisterClass
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:169
DecodeGPRF32RegisterClass
static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:101
LLVMInitializeRISCVDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
Definition: RISCVDisassembler.cpp:67
DecodeGPRNoX0RegisterClass
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:180
decodeFRMArg
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:403
DecodeSR07RegisterClass
static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:227
decodeRVCInstrRdRs1UImm
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:496
TRY_TO_DECODE_AND_ADD_SP
#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC)
Definition: RISCVDisassembler.cpp:601
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:125
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:75
decodeVMaskReg
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:310
decodeUImmNonZeroOperand
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:345
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:168
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:165
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:84
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:217
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:108
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:199
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:211
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:207
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
llvm::MCInstrDesc::operands
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:135
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:142
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:149
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:108
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:121
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:144
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint32_t
uint64_t
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:419
llvm::support::endian::read16le
uint16_t read16le(const void *P)
Definition: Endian.h:422
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:425
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:878
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