RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Introduction to Static Timing Analysis with
PrimeTime
Jiuling Tang
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Timing Analysis
Mainly check every flip-flop meets its setup and hold time requirements
Data1
Clk
_
Q
CLK
Logic
Data2
_
Q
CLK
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Data and Clock Waveforms
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Flip-Flop (FF) Setup and Hold Time
Requirement
Tclock 2 q + Tlog ic _ max + Tsetup < Tperiod + Tskew
Tclock 2 q + Tlog ic _ min > Thold + Tskew
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Timing Analysis Methods
Dynamic Timing Analysis
Running SPICE simulation
Or running exhaustive gate-level simulations with SDF
Accurate
Slow
Static Timing Analysis (STA)
Tools, like Synopsys PrimeTime
Less accurate, but good enough
Faster
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Synopsys PrimeTime (PT)
The most trusted and advanced timing sign-off solution for gate-level
STA tool
Analysis of up to 100 - million gate design
Accurate to within 5% of SPICE
Delay calculation by using parasitics information for accurate
interconnect analysis
Advanced modeling
Interface Logic Models (ILM) for hierarchical static timing analysis
and sign-off
Extracted Timing Models (ETM) in .lib format for cell-based reusable
IP and physical design flows
Quick Timing Models (QTM) for top-down design
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
How STA Works
Find out all valid paths in the design
Use technology libraries characterized by SPICE to calculate the delay of
each path
Check all the path delays to see if setup and hold time have been meet
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Timing Paths
Start points
Inputs
Clock pins of flip-flops
End points
Outputs
Data input pins of flip-flops
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Timing Paths (continued)
Data1
Logic
_
Q
CLK
Logic
Data2
_
Q
CLK
Logic
DataOut1
Clk
DataIn2
Logic
DataOut2
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Path Delay
Sum up all the cell and net delays along a timing path
Cell delay
-Depend on input transition and output load
-Use Non Linear Delay Model (NLDM) before and after
layout
Net delay
-From wire load model before layout
-From parasitic extraction after layout
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Clock Jitter, Skew, Transition, and Latency
Before layout
Have to estimation skew, transition and latency
set_clock_uncertainty
set_clock_transition
After layout
From actual clock tree
set_propgated_clock
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Three Types of STA Analysis
Single
Check for setup time only
Use one process, voltage, and temperature (PVT) condition
Best case (BC) and worst case (WC)
Check both setup and hold time
BC uses one PVT condition
WC uses another one PVT condition
On chip variation
Conservative analysis, Check both setup and hold time
For setup checks, it considers a slow launch clock path and slow data
path, but a fast capture clock path. hold checks, it does the opposite
Use two PVTs to represent variation across a die
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Tool Command Language (TCL)
TCL is the command interface to PT
TCL is an interpreted, programmable, and scriptable language
TCL also widely used by other EDA tools, like Design Compiler, Physical
Compiler, PT, ModelSim, Xilinx ISE
PT only has TCL mode
For more information about PT TCL commands, just type help at PT
prompt
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
STA Steps of PT
[Link] required files
[Link] the design
[Link] constraint coverage
[Link]
[Link] reports
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Required Input Files
PT setup file: .synopsys_pt.setup
Technology libraries
Gate-level netlist, support format
db
Verilog
VHDL
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Set Up of PT
Set up the search_path variable
A list of paths used to locate the design, libraries and other files
needed by PT
set search_path {. ./vhdl ./scripts}
Set up the link_path variable
Places where PT can find designs and libraries when linking the
design
set link_path {* tech_lib.db [Link]}
It is same as DC link_library
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Reading Design into PT
Use following commands to read designs into PT
read_db
read_vhd
read_verilog
Manually read all files
Read top module first and PT will read all sub-module automatically
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Resolving Reference
PT uses command link_design resolves all reference in a design using
the link_path.
If fails, it will find and replace the space holder with actual library cells or
sub designs referenced specified in search_path
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Constraining internal FF to FF Timing Paths
Create a clock constraints all internal FF to FF timing paths. like
create_clock period ClockPeriod [get_ports CLK]
If consider clock skew and jitter, use clock uncertainty to model them
set_clock_uncertainty setup number [get_ports CLK]
Uncertainties between synchronous clocks
set_clock_uncertainty setup 0.5 -from [get_clocks Clock1] -to
[get_clocks Clock2]
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Clock Latency and Transition before Layout
Network latency due to clock tree insertion
Set_clock_latency max 1 [get_clocks Clock]
Source latency due to clock source not very clock
Set_clock_latency source max 1 [get_clocks Clock]
Clock transition
set_clock_transition 0.2 [ all_clocks]
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Clock Source and Network Latency
Source: Synopsys
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Clock Latency and Transition after Layout
Network latency due to clock tree insertion
Set_propagated _clock [all_clocks]
Source latency due to clock source not very clock
Set_clock_latency source max 1 [get_clocks Clock]
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Clock Source and Network Latency
Source: Synopsys
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Generated Clock
If there are generated clocks inside the design, use
create_generated_clock -source clock -name div2clock -divide_by
2 [get_pins div2reg/regout]
(Source: Altera)
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Constraint Input Paths
To specify the maximum arrival time of external data with respect to a
launching clock and inputs, need to set input delay. For example
Set_input_delay max 2 clock Clock [get_inputs Datain]
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Set Input Delay
Source: Synopsys
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Driving cell for input ports
To calculate the timing of inputs cells, use set_driving_cell to specify
external driving cell for input ports
set_driving_cell lib_cell buf1 [get_ports DataIn]
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Constraint output Paths
To specify the setup time of an output with respect to a capture clock,
use set output delay. For example
set_output_delay max 2 clock Clock [get_outputs DataOut]
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Output Delay
Source: Synopsys
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Seting Load for Output Ports
To calculate the timing of outputs cells, use set load to specify external
load for output ports
set_load 5 [get_ports DataOut]
Or set LOAD [expr [load_of fir_core/INV/A]*3]
set_load $LOAD [get_ports DataOut]
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
False Paths
False paths:
logically impossible
Between asynchronous clocks
PT commands used to specify false paths
set_false_path from [get_clocks ClkA] to [get_clocks ClkB]
set_clock_groups asynchronous name ASYNC group ClkA
group ClkB
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
An Example of False Path
Source: Synopsys
Its logically impossible from mux1/A to mux2/A or from mux1/B to mux2/B
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Multi-cycle Paths
Multi-cycle paths:
More than 1 clock cycle
PT commands used to specify multi-cycle paths
set_multicycle_path 10 setup to [get_pins fir_reg[*]/D]
set_multicycle_path 9 hold to [get_pins fir_reg[*]/D]
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Specifying Operating Condition
Setting operating condition by using
set_operating_conditions analysis_type bc_wc max WC_OC min
BC_OC
set_operating_conditions analysis_type on_chip_variation max
WC_OC min BC_OC
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Design Rules
Restriction imposed on the use of library cells by technology vendors.
Vendors impose design rules that restrict how many cells are connected
to one another based on capacitance, transition, and fanout
Design rules has high priority of all. Related commands are
set_max_capacitance
set_max_transition
set_max_fanout
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Checking Design Constraints
check_timing shows problems like:
Missing clock definition
Ports no input delay or output delay
Input or output delays without a reference clock
Combinational feedback loops
Unconstrainted endpoints for setup
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Performing STA
Three techniques for performing STA
1. Generating constraint report
report_constraint all
2. Generating bottleneck report
report_bottleneck
3. Generating timing report
report_timing
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Constraint Analysis
report_constraints give us following violations in design
Setup/hold
DRC
Pulse width
report_constraints all_violators shows all the violations and where
violations are
Things need to investigate
How many end points violate timing? End points are registers or
outputs
What is the largest violation?
How many DRC violations?
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Bottleneck Analysis
report_bottleneck shows the cells involved in multiple violations
Identify submodule containing the bottleneck cells and refine the module
and resynthesizing them
Replace the submodule with new one
Regenerate constraint report
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Timing Report
report_timing finds all the timing paths
Analyzes each path for timing twice for both rising and falling edges
Shows critical paths for each clock group
From above information, we investigate the causes of the violations due
to
Poor partition
Excessive net fanout
Large capacitance load
Slower transition time
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Summary
Source: Synopsys
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR
Demos
