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Verilog: Following Is The Verilog Code

This document contains Verilog and VHDL code that implements a 3-bit to 8-bit multiplexer (mux). The Verilog code uses a case statement to assign a unique 8-bit value to the output res based on the 3-bit input sel. Similarly, the VHDL code uses a conditional assignment to set res to a different value depending on the value of sel. Both codes are examples of how to write a basic multiplexer in the Verilog and VHDL hardware description languages.

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Varadha Rajan
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84 views2 pages

Verilog: Following Is The Verilog Code

This document contains Verilog and VHDL code that implements a 3-bit to 8-bit multiplexer (mux). The Verilog code uses a case statement to assign a unique 8-bit value to the output res based on the 3-bit input sel. Similarly, the VHDL code uses a conditional assignment to set res to a different value depending on the value of sel. Both codes are examples of how to write a basic multiplexer in the Verilog and VHDL hardware description languages.

Uploaded by

Varadha Rajan
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

Verilog

Following is the Verilog code.

module mux (sel, res);


  input [2:0] sel;
  output [7:0] res;
  reg [7:0] res;

  always @(sel)
  begin
    case (sel)
      3'b000 : res = 8'b00000001;
      // unused decoder output
      3'b001 : res = 8'bxxxxxxxx;
      3'b010 : res = 8'b00000100;
      3'b011 : res = 8'b00001000;
      3'b100 : res = 8'b00010000;
      3'b101 : res = 8'b00100000;
      3'b110 : res = 8'b01000000;
      default : res = 8'b10000000;
    endcase
  end
endmodule

On the contrary, the following description leads to the inference of a 1-of-8 decoder.

IO pins Description

s[2:0] Selector

res Data Output

VHDL

Following is the VHDL code.

library ieee;
use ieee.std_logic_1164.all;

entity dec is
  port (sel: in std_logic_vector (2 downto 0);
        res: out std_logic_vector (7 downto 0));
  end dec;
architecture archi of dec is
  begin
    res <= "00000001" when sel = "000" else
            "00000010" when sel = "001" else
            "00000100" when sel = "010" else
            "00001000" when sel = "011" else
            "00010000" when sel = "100" else
            "00100000" when sel = "101" else
  -- 110 and 111 selector values are unused
            "XXXXXXXX";
end archi;

Verilog

Following is the Verilog code.

module mux (sel, res);


  input [2:0] sel;
  output [7:0] res;
  reg [7:0] res;

  always @(sel or res)


  begin
    case (sel)
      3'b000 : res = 8'b00000001;
      3'b001 : res = 8'b00000010;
      3'b010 : res = 8'b00000100;
      3'b011 : res = 8'b00001000;
      3'b100 : res = 8'b00010000;
      3'b101 : res = 8'b00100000;
      // 110 and 111 selector values are unused
      default : res = 8'bxxxxxxxx;
    endcase
  end
endmodule

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