CCS Technology

Synopsys Interoperability Forum November 9, 2005 Bill Mullen Vice President of Engineering Synopsys, Inc.

Composite Current Source (CCS)

Timing

Timing

Noise

Power

2005 Synopsys, Inc. (2)

Delay Calculation Requirements

Driver Model: drive arbitrary interconnect, including
high-impedance nets Receiver model: complex input capacitance Efficient characterization Vdd & Temperature scaling for IR drop, multi-Vdd, DVFS, corners

load1 driver
Driver Model

Receiver Model

load2

2005 Synopsys, Inc. (3)

NLDM Based Driver/Receiver Models

Cinp + v(t) Rd Reduced-Order Network Model Input cap single value

Driver Model

Ramp voltage source, fixed drive resistance Very fast accurate for most nets Limited accuracy for high impedance networks with large drivers (RC-009)

Receiver Model
min/max rise/fall input caps Doesnt model capacitance
variation during transition

2005 Synopsys, Inc. (4)

Basics of CCS Timing

Driver model i(t,v) Nonlinear Current Source Receiver model
C1, C2 vary with Input slew Output load

C1

C2

Rise vs. fall State of cell

Load1

Driver Load2

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Characterization for NLDM

Pin Capacitance
input slew 0.7 0.5 0.2 0.1
.023 .047 .065 .078 .091

Cell Delay / Slew Tables

input slew 0.7
3.31 2.72 2.22 1.31 3.61 3.12 2.54 1.75 3.98 3.43 2.72 1.99 4.12 3.82 3.11 2.31 5.32 4.25 3.47 2.77

Cinp (single value)

0.5 0.2 0.1

.023 .047 .065 .078 .091

output cap

output cap

Measure current and voltage at input pin for receiver model

Measure cell delay and output slew

2005 Synopsys, Inc. (6)

Characterization for CCS Timing

Receiver Model
input slew 0.7 0.5 0.2 0.1
C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2

Driver Model
input slew 0.7 0.5 0.2 0.1
.023 .047 .065 .078 .091

.023 .047 .065 .078 .091

output cap

output cap

Measure current and voltage at input pin for receiver model

Measure current through load cap for driver model

2005 Synopsys, Inc. (7)

CCS Receiver Model Advantage

CCS Receiver Model matches
both delay & slew

One Cinp value is insufficient

Miller effect at input pin of inverter

Input cap: single value

C1 Cinp C2

CCS
Receiver model

2005 Synopsys, Inc. (8)

Vdd and Temperature

CCS Timing enables high accuracy delay calculation for wide range of Vdd and Temperature For power-aware design styles:
Single Vdd Multiple Vdd Dynamic Voltage & Frequency Scaling (DVFS) lib_1.2v.db lib_1.0v.db lib_0.8v.db
Separate CCS Libraries

Advanced analysis including IR Drop effects

What is scaled:
Driver model Receiver model Timing constraints: setup, hold, recovery, removal, MPW

Straightforward characterization

2005 Synopsys, Inc. (9)

Constraint Arcs: Vdd & Temperature

Constraint arc (timing check) values depend on
Vdd and Temperature CCS Timing supports nonlinear scaling of constraint arcs
Setup vs. Vdd
110

D CK

105

tsetup
setup (ps)

100 95 90 85 80 75

CK D
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70 65 60 0.8 0.85 0.9 0.95 1 Vdd (V) 1.05 1.1 1.15 1.2

CCS Timing Results

Results: STARC, TSMC

STARC
3500
900 Del (HSPI E vs PT-lberty, ay C i PT-C C S)

Major Foundry
2% vs. HSPICE
lberty i -3% +3% CC S

Del (HSPI E vs PT-lberty, ay C i PT-C C S)

3000

850

800

2500 lberty, S[ps] i CC

750

lberty, C S [ps] i C

lberty i -3% +3% CC S

700

2000

650

600 600

HSPI CE[ps] 650 700 750 800 850 900

1500

1000

500

3% vs. HSPICE
HSPI CE[ps] 0 500 1000 1500 2000 2500 3000 3500

PrimeTime2004.12 with STARC 90nm CCS liberty libraries Error : < 3% vs. HSpice

PrimeTime2005.06 with 90nm CCS liberty libraries Error : < 2% vs. HSpice

2005 Synopsys, Inc. (12)

Customers Demonstrate CCS Accuracy

CCS Accuracy v s. HSPICE
5

+/-2%
6,000

CCS & NLDM vs. HSPICE

+/-3%

5,000

4,000

3 C C S [ns]
CCS -2%
H SP IC E
NLDM

3,000

CCS +3% -3%

+2%

2,000

1
1,000

0 0 1 2 Hspice [ns] 3 4 5

0 1,000 2,000 3,000 Prime Time 4,000 5,000 6,000

90nm Library
Major Electronics Firm in Asia
2005 Synopsys, Inc. (13)

65nm Library
Leading Global IDM

CCS Timing Summary

High accuracy delay and slew calculation

Advanced driver and receiver modeling Results within 2% of SPICE Powerful scaling for Vdd and Temperature

No impact on analysis runtime Easy and efficient characterization Industry Support

ARM, TSMC, Virage Logic, STARC, Library Technologies, Synopsys NanoChar

2005 Synopsys, Inc. (14)

Composite Current Source (CCS)

Noise

Timing

Noise

Power

2005 Synopsys, Inc. (15)

Noise Analysis
Aggressor Failure Analysis

0 Victim

Calculate Glitch

Propagated Glitch

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Noise Modeling Requirements

Accurate model to support:

Noise bump calculation Noise propagation Driver weakening (combination of propagated and injected bumps) Vdd and Temperature scaling

Characterization should be fast and cover a broad set of cell types Model must enable efficient calculation in analysis and implementation tools

2005 Synopsys, Inc. (17)

NLDM Noise Modeling in Liberty

Aggressor Noise Immunity Curve

0 Victim

I/V Curve
Noise Propagation

Table-based noise immunity and propagation characterization require extensive circuit simulation
2005 Synopsys, Inc. (18)

Introducing CCS Noise

Faster Characterization:
100X faster characterization vs. NLDM Noise
Much less circuit simulation is needed Typical 90nm library in under 4 hours on 10 cpus

High Accuracy:
Accurately models noise propagation and driver weakening Accurate voltage and temperature scaling using the same scaling mechanism as CCS Timing Same accurate receiver modeling as CCS Timing

2005 Synopsys, Inc. (19)

CCS Noise: Cell Model

Inverter: 1 stage cell DFF: multi-stage cell
CCS-N CCS-N D CCS-N Q

AND: 2 stage cell

CK CCS-N CCS-N CCS-N CCS-N

First and last transistor stages are modeled

2005 Synopsys, Inc. (20)

Arc and Pin CCS Noise Models

Input stage: Noise immunity Output stage: Driving strength Arc: Immunity + Driving Strength + Noise Propagation For paths of one or two stages
Pin-Based Model Arc-based Model
CCS-N CCS-N CCS-N D CCS-N CK CCS-N CCS-N Q

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Arc-Based Example: AND2

A1 Z N_7

A1

CCS-N CCS-N CCS-N Z

A2

A2

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AND2 Liberty Syntax

pin(Z) { direction : output; timing() { related_pin : "A1";

ccsn_first_stage() { /* A1 to N_7 */ } ccsn_last_stage() { /* N_7 to Z */ }

}

timing() { related_pin

: "A2";

ccsn_first_stage() { /* A2 to N_7 */ } ccsn_last_stage() { /* N_7 to Z, copy of the above */ }

} }

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CCS Noise Stage Contents

Each CCS Noise stage has three components: 1. DC Current Table CCS Noise stage 2. Dynamic Behavior Information 3. Parameters

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Characterization: DC Current Table

DC Current table represents output current as a function
of two variables Vin: Input voltage Vout: Output voltage A fast DC sweep simulation is used to capture data

Vin
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+ -

+ -

Vout

Characterization: Dynamic Behavior

Small number of transient simulation runs
Inputs: A few ramps and a few glitches Output response is used to derive the dynamic behavior of the stage

2005 Synopsys, Inc. (26)

Noise Propagation Accuracy

CCS Noise accurately models dynamic effects such as the impact of charging/discharging of internal nodes Propagated noise
waveform (HSPICE)
1

Voltage (V)

Internal Nodes

0.5

Propagated noise waveform (PTSI)

Input noise waveform 0 (HSPICE)

0 100 200 Time (ps) 300 400

2005 Synopsys, Inc. (27)

CCS Noise Bump Height Correlation

aggressor (quiet) victim aggressor
1.2 1.2

Noise Bump Calculation (Node A)

PTSI Noise Height (V)

Noise Propagation (Node B)

PTSI Noise Height (V)

0.8

0.8

0.6

0.6

0.4

0.4

0.2

0.2

0.2

0.4

0.8 0.6 SPICE Noise Height (V)

1.2

0.2

0.4

0.8 0.6 SPICE Noise Height (V)

1.2

2005 Synopsys, Inc. (28)

Noise Propagation Correlation

1.2 1.2

10%
1 1

PTSI Noise Height (V)

0.8

PTSI Noise Height (V)

0 0.2 0.4 0.8 0.6 SPICE Noise Height (V) 1 1.2

0.8

0.6

0.6

0.4

0.4

0.2

0.2

0.2

0.4

0.8 0.6 SPICE Noise Height (V)

1.2

NLDM Noise

CCS Noise

2005 Synopsys, Inc. (29)

CCS Noise Fast Characterization

Library Technology Lib1 90-nm Lib2 90-nm Lib3 90-nm Lib4 90-nm Lib5 90-nm Lib6 65-nm Number of cells 595 747 593 541 1304 766 Characterization time on 10 CPUs 1.5 hrs 2 hrs 4 hrs 1 hr 4 hrs 3 hrs

2005 Synopsys, Inc. (30)

CCS Noise Summary

Very good customer beta test results Fast characterization
Typical library in under 4 hours on 10 cpus For large blocks, only need to characterize boundary stages

Fast calculation no measurable overhead during noise analysis High Accuracy

Noise propagation and driver weakening Voltage and temperature scaling

2005 Synopsys, Inc. (31)

Composite Current Source (CCS)

Power

Timing

Noise

Power

2005 Synopsys, Inc. (32)

Power Library Requirements

Address needs of Multi-Voltage designs

Multi-Rail cells (Vdd, Vss) Non-zero ground rail MTCMOS (power gating)

Static and dynamic rail analysis

Support accurate voltage (IR) drop calculation

Single library / model for all power related applications Fast and easy library characterization

2005 Synopsys, Inc. (33)

Power Gating (MTCMOS)

Reduce Leakage by turning block off
Vdd Vsleep

Fine Grain: Sleep transistor within each cell IN Sleep

LVt

MTCMOS

OUT

Block A

VirtualVdd

Block B
Sleep-mode
Power switch control

Block C

Coarse Grain: Sleep transistor for entire block

VDD

VSS VDD

Challenge: Analyze in-rush current when block turns on

2005 Synopsys, Inc. (34)

INTERNAL VSS

Introducing CCS Power

Switching current waveform for each power or ground pin
Finer time resolution Full Multi-Voltage support

Equivalent parasitics as seen from the power network

Allows fast yet accurate rail analysis

Support for macro power modeling for memory and IP Unified library model for power optimization, power analysis, rail analysis Fast and easy to characterize

2005 Synopsys, Inc. (35)

Characterization for NLPM

Liberty Non-Linear Power Model

Internal Energy per transition

3.31
0.7 input 0.5 slew 0.2 0.1
2.72 2.22 1.31 3.61 3.12 2.54 1.75 3.98 3.43 2.72 1.99 4.12 3.82 3.11 2.31 5.32 4.25 3.47 2.77

.023 .047 .065 .078 .091

Leakage power per state

output cap

2005 Synopsys, Inc. (36)

Characterization for CCS Power

Dynamic Current Waveform per transition per Rail 0.7 0.5

i(t)

0.2

Leakage current per state per rail

0.1 input .023 .047 .065 .078 .091 slew output cap

Can characterize CCS Power switching information concurrently with CCS Timing
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CCS Power Characterization

HSPICE Simulation: AND gate with rising input

Power pin (Vdd) current Ground pin (Vss) current

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Advantages: Time Resolution

Captures complete
power and ground pin current waveforms
Charge/energy can be calculated by integrating current

I i + I i 1 I n (t n t n 1 ) Idt 2 (ti ti 1 ) + ln(I n1 I n ) i =1 0

n

2005 Synopsys, Inc. (39)

Dynamic Rail Analysis

Compute instance-specific voltage drop at
all power/ground pins

Requires cell model for switching and nonswitching cases

VDD1

Cpar

Rpar

GND

2005 Synopsys, Inc. (40)

Equivalent Parasitics for NonSwitching Case

Essential for accurate rail analysis additional decoupling cap Cpar per input state for each power or ground pin Rpar per input state for each power or ground pin to each output

IN1 OUT Cload IN2 Cint Cpar

Rpar

Cload

Equivalent Parasitics
2005 Synopsys, Inc. (41)

CCS Power Summary

Single Power Model For All Power Applications: Accurately Models:
Power Optimization, Dynamic Rail Analysis, Power Analysis Transient current during switching Equivalent parasitics for non-switching case Leakage current Multi-Voltage designs
Multi-rail cells Non-zero ground rail

Characterized concurrently with CCS Timing

MTCMOS: fine-grain or coarse-grain

2005 Synopsys, Inc. (42)

CCS Summary
Continuing With A Tradition Of Innovation

CCS - Next Generation Modeling Technology

Open Source Unified Model For Timing, Noise and Power Higher Accuracy as Needed By 90nm and Below

Easy and Efficient Library Characterization Complete Ecosystem: Models, Format, Characterization

Timing

Noise

Power

2005 Synopsys, Inc. (43)

Technical Collateral Material

Technical collateral material for CCS is available on:
www.synopsys.com/products/solutions/galaxy/ccs/cc_source.html

It includes:
CCS Backgrounder White Papers Format Specification FAQ

2005 Synopsys, Inc. (44)