RTL Design
What is RTL Design
RTL(Register Transfer Level) design refers to the designing digital circuits to
produce synthesizable hardware models and models digital circuits at higher
level of abstraction using HDL(Hardware Description Language) like
Verilog/VHDL/SystemVerilog.
Code written in verilog Synthesized digital design
module AND_2(output C, input A, B);
reg C;
and(A, B, C);
endmodule
Categories of RTL Design
➢ FPGA Design:
➢ FPGA hardware is programmable and can be used for multiple
applications. Designers can code entirely digital applications and
implement on FPGA.
➢ ASIC Design:
➢ ASIC Design is mainly done for specific applications like autonomous
vehicles, data centers where a lot more optimization is required and
some hardware needs to be implemented in analog as well
Scope of Jobs in RTL design
➢ It’s a bit tough if you are not from premium college, but nothing is
impossible ☺
➢ FPGA design is more open to freshers as compared to ASIC design.
Scope of Work in RTL design
➢ Understand the specifications of your block and how is it going to interact with other
blocks inside the chip.
➢ Work with verif teams to resolve design bugs if any.
➢ Run checks to check if design is synthesizable and follow good RTL coding guidelines.
➢ Run checks to identify if metastability concerns arising due to CDC (clock domain
crossing), RDC (reset domain crossing), power gating etc have been taken care of in
design or not.
➢ Write synthesis constraints so that synthesis team can use them and implement the correct
netlist like take timing constraints into account to add buffers and stuff.
➢ Work with DFT (design for testability) team to make sure that design pins and internal
nodes can be checked for stuck at faults (nodes tied off to zero or one because of
manufacturing issues) using external patterns.
Skills required for RTL Engineer
➢ Basic digital design blocks like multiplier, divider, sequence detector, clock
gating cell, clock domain synchronizer, reset synchronizer, edge detector,
mealey and moore machines, fifo, counters, level shifter, isolation cells etc,
clock domain crossing , reset domain crossing
➢ Reference: Digital Logic Design By Morris Mano
➢ https://www.scribd.com/document/342765064/Digital-Logic-RTL-Verilog-Interview-
Questions-Preview
➢ Verilog
➢ Reference: Verilog HDL: A Guide to Digital Design and Synthesis By Samir Palnitkar
➢ Scripting in Perl/ Python and Shell
➢ Logic Synthesis
➢ Basics of STA
Free Online Courses
➢ Digital systems basics and vhdl basics
https://www.coursera.org/learn/digital-systems#syllabus
➢ FPGA design
https://www.coursera.org/learn/intro-fpga-design-embedded-
systems#syllabus
https://www.coursera.org/learn/fpga-hardware-description-
languages#syllabus
➢ Verification using System Verilog
https://www.udemy.com/course/soc-verification-systemverilog/
Clock domain crossing
CDC happens when signal goes from one clock domain to another clock domain. As shown in
below diagram if aclk changes close to bclk, then adat will have setup violation for second flop
and hence make destination flop metastable.
Writing RTL for clock domain crossing
and how to check them
➢ You need to have synchronization cells and FIFOs inside the design to
overcome CDC.
➢ There are multiple ways to check for CDC:
➢ Manual review of the code (in below code signal is going from ck1 to ck2)
Always (@ck1)
out1 <= in1;
Always (@ck2)
Out <= out1;
➢ Use dedicated tools like Spyglass, Meridien etc to catch CDC issues.
➢ Run functional simulations with timing
Low Power design in Frontend
➢ Power gating : Turn off the power supply of some blocks which may not
be required in a particular functional mode. Entire chip is divided into
multiple power domains
➢ Clock gating: Clock of particular set of flops can be turned off using an
external enable. This can be done inside a particular power domain itself,
like some debug logic can be turned off during functional mode for a
particular IP.
What is linting?
➢ Linting is a process of running lint checks, that is static checks written to catch potential bugs inside the
design which can lead to functional failures and synthesis issues later in design cycle. Some of the
bugs caught by Lint tool area:
➢ Unsynthesizable constructs
➢ Unintentional latches
➢ Simulation synthensis mismatches
➢ Undriven signals
➢ Race conditions
➢ Incorrect usage of blocking and non-blocking assignments
➢ Case statement style issues
➢ Set and reset conflicts
➢ Out-of-range indexing
Lint check example
module flop_test (in,clk,rst,out)
Input in,clk,rst;
reg out;
output out;
d_flop d1(.d(in),.clk(),.rst(),.out(out));
Endmodule
In above example, designer forgot to connect clock and reset of instantiated
module, therefore instantiated module wont work properly and design will see
simulation failures. This can be fixed by RTL designer itself before it goes to
verification team for testing. A lot of time can be saved.
Hands on experience in Lint and CDC
➢ Industry tools used for Lint: Spyglass, Ascent Lint, LEDA
➢ Not aware of any open source EDA tools. Perhaps, at this stage you can
only understand what these checks do, hands on is difficult without any
tools.
➢ EDA tools that can be explored for backend and synthesis:
https://www.udemy.com/course/vsd-a-complete-guide-to-install-open-
source-eda-tools/
Is System Verilog used for Front end
design?
Yes..
➢ Used for RTL design
➢ Used for writing assertions
➢ Used for verification
How is it better than Verilog?
https://academic.csuohio.edu/chu_p/rtl/fpga_mcs_vlog_book/SystemVerilog
%20vs%20Verilog%20in%20RTL%20design.pdf
https://www.youtube.com/watch?v=pN1PzLI8SG0
