EXPERIMENT 01
Object - Transient analysis and simulation of bjt inverter.
Software used - PSPICE
Theory-
The voltage transfer characteristic of a BJT inverter (Fig. 1) is consisting of three
regions, the cutoff
When vi is low, the active where the characteristic has a slope and the saturation
region where the
Collector current is the maximum and the output voltage is low equal to VCEsat.
1. Cut-off region.
2. Forward Active region.
3. Saturation region.
BJT Inverter can be best expressed by its voltage transfer characteristic (VTC) or DC
transfer characteristic. That relates the output voltage to the input one.
If:
1) Vi = Vol, Vo = Voh = Vcc: (VTC) or DC Transfer Characteristic The transistor is OFF.
2) Vi = Vil: The transistor Begins to turn on.
3) Vil < Vi < Vih The transistor is in forward active region and operates as Amplifier.
4)Vi = Voh The transistor will be deep is saturation, Vo = Vce(sat).
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Circuit diagram-
Netlist description-
Q_Q1 N00087 N00493 0 Q40235
R_R1 N00087 N00200 1k
V_V2 N00493 0
+PULSE 0 5 0 0 0 50ns 100ns
V_V1 N00200 0 5Vdc
Output waveform-
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EXPERIMENT 02
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Object- Transient analysis and simulation of NMOS inverter.
Software used- PSPICE
Theory:n
Single transistor, pulls signal low
Inverter Operation
• Plus signal input turns transistor on
• Ground is connected to output
• Thus a 1 (+) in gives 0 (Ground) out
• A 0 input opens transistor and output is pulled high by resistor
• Resistor dissipates heat
• Asymmetric rise/fall times.
OUTPU
INPUT
T
A NOTA
0 1
1 0
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Circuit diagram-
Net list Description-
M_M1 N00063 N00343 0 0 M2N6659
R_R1 N00063 N00131 100
V_V2 N00343 0
+PULSE 0 5 0 0 0 50ns 100ns
V_V1 N00131 0 5Vdc
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Output waveform
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EXPERIMENT 03
Object- Transient and simulation analysis of CMOS nor gate .
Software used- PSPICE
Theory-
• The circuit below has two inputs and one output.
• Whenever at least one of the inputs is high, the corresponding N-type transistor will
be closed while the P-type transistor will be open.
• Consequently, the output voltage will be low.
• Conversely, if both inputs are low, then both P-type transistors at the top will be
closed circuits and the N-type transistors will be open.
• Hence, the output voltage is high.
• The function of this gate can be summarized by the following table:
V1 V2 Output
Low Low High
Low High Low
High Low Low
High High Low
• If logical 1's are associated with high voltages then the function of this gate is called
NOR for negated OR.
• Again, there is never a conducting path from the supply voltage to ground.
NOR Circuit and Standard Symbol
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Circuit diagram:
Net list description-
M_M1 N00138 N00382 0 M2N6659
M_M2 N00138 N00310 0 0 M2N6659
V_V3 N00310 0
+PULSE 0 5 0 0 0 50ns 100ns
M_M3 N00107 N00310 N00569 N00569 M2N6806
V_V1 N00569 0 5Vdc
M_M4 N00138 N00382 N00107 N00107 M2N6806
V_V2 N00382 0
+PULSE 0 5 0 0 0 50ns 100ns
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Output waveform-
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EXPERIMENT 04
Object- Transient and simulation analysis of NAND gate .
Software used- PSPICE
Theory-
• The circuit below has two inputs and one output.
• Whenever at least one of the inputs is low, the corresponding P-type transistor
will be conducting while the N-type transistor will be closed.
• Consequently, the output voltage will be high. Conversely, if both inputs are
high, then both P-type transistors at the top will be open circuits and both N-
type transistors will be conducting.
• Hence, the output voltage is low.
• The function of this gate can be summarized by the following table:
V1 V2 Output
Low Low High
Low High High
High Low High
High High Low
• If logical 1's are associated with high voltages then the function of this gate is
called NAND for negated AND.
• Again, there is never a conducting path from the supply voltage to ground
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FIG 1: CMOS NAND GATE
CIRCUIT DIGGRAM:
NET LIST DESCRIPTION :
M_M1 N00147 N00915 0 0 M2N6659
M_M2 N00201 N01003 N00147 N00147 M2N6660
V_V1 N00278 0 5Vdc
V_V6 N00915 0
+PULSE 0 5 0 0 0 50ns 100ns
M_M4 N00201 N01003 N00278 N00278 M2N684
V_V4 N01003 0
+PULSE 0 5 0 0 0 50ns 100ns
M_M5 N00201 N00915 N00278 N00278 M2N6845
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OUTPUT WAVEFORM
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EXPERIMENT 05
Object- Transient analysis and simulation of CMOS inverter.
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Software used- PSPICE
Theory- CMOS inverters (Complementary NOSFET Inverters) are some of the most
widely used and adaptable MOSFET inverters used in chip design. They operate with
very little power loss and at relatively high speed.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and
gate terminals, a supply voltage VDD at the PMOS source terminal, and a ground
connected at the NMOS source terminal, were VIN is connected to the gate
terminals and VOUT is connected to the drain terminals.(See diagram)
The circuit below is the simplest CMOS logic gate.
• When a low voltage (0 V) is applied at the input, the top transistor (P-type) is
conducting (switch closed) while the bottom transistor behaves like an open
circuit.
• Therefore, the supply voltage (5 V) appears at the output.
• Conversely, when a high voltage (5 V) is applied at the input, the bottom
transistor (N-type) is conducting (switch closed) while the top transistor
behaves like an open circuit.
• Hence, the output voltage is low (0 V).
• The function of this gate can be summarized by the following table:
Input Output
High Low
Low High
• The output is the opposite of the input - this gate inverts the input.
• Notice that always one of the transistors will be an open circuit and no
current flows from the supply voltage to ground.
Fig: Transistor "switch model
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The switch model of the MOSFET transistor is defined as follows:
MOSFET Condition MOSFET State of MOSFET
NMOS Vgs<Vtn OFF
NMOS Vgs>Vtn ON
PMOS Vsg<Vtp OFF
PMOS Vsg>Vtp ON
When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging
VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is "on: draining
the voltage at VOUT to logic low.
Net list description-
M_M1 N00263 N00282 0 0 M2N6659
V_V1 N00385 0 5Vdc
M_M2 N00263 N00282 N00385 N00385 M2N6806
V_V2 N00282 0
+PULSE 0 5 0 0 0 50ns 100ns
Circuit diagram
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Output waveform-
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EXPERIMENT NO
Aim:Analysis of frequency response of Common Source amplifiers.
Software Used:-Pspice
Theory- In electronics, a common-source amplifier is one of three basic
single-stage field-effect transistor (FET) amplifier topologies, typically used as
a voltage or transconductance amplifier. The easiest way to tell if a FET is
common source, common drain, or common gate is to examine where the
signal enters and leaves. The remaining terminal is what is known as
"common".
Voltage gain in low- and high-frequency bands is smaller than midband
gain due to effects of coupling/bypass and transistor capacitors,
respectively. Often CS (bypass capacitor) determines the low 3dB
frequency fL, then:
fL=gm/2*pi*Cs
calculation of the corresponding high 3dB frequency fH.
Fh=1/2*pi.CL.(RL||RD||r0)
Fig CS Amplifier
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Circuit Diagram:
Output:-
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