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SEMICONDUCTOR TECHNICAL DATA by MTP3N50E/D

   
 

 
   Motorola Preferred Device

   

N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
This advanced high voltage TMOS E–FET is designed to 3.0 AMPERES
withstand high energy in the avalanche mode and switch efficiently. 500 VOLTS
This new high energy device also offers a drain–to–source diode RDS(on) = 3.0 OHMS
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability 
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients. D
• Avalanche Energy Capability Specified at Elevated
Temperature
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External G
Zener Transient Suppressor — Absorbs High Energy in the
Avalanche Mode S
• Source–to–Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode

CASE 221A–06, Style 5

TO–220AB

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit
Drain–Source Voltage VDSS 500 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc
Gate–Source Voltage — Continuous VGS ± 20 Vdc
Gate–Source Voltage — Non–repetitive (tp ≤ 50 µs) VGSM ± 40 Vpk

Drain Current — Continuous ID 3.0 Adc

Drain Current — Pulsed IDM 10

Total Power Dissipation @ TC = 25°C PD 50 Watts

Derate above 25°C 0.4 W/°C

Operating and Storage Temperature Range TJ, Tstg – 65 to 150 °C

UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C)

Single Pulse Drain–to–Source Avalanche Energy — TJ = 25°C WDSR (1) 210 mJ
Single Pulse Drain–to–Source Avalanche Energy — TJ = 100°C 33
Repetitive Pulse Drain–to–Source Avalanche Energy WDSR (2) 5.0

THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case° RθJC 2.5 °C/W
— Junction to Ambient° RθJA 62.5
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
(1) VDD = 50 V, ID = 3.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

 Motorola TMOS
Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1
MTP3N50E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V(BR)DSS 500 — — Vdc
(VGS = 0, ID = 0.25 mA)

Zero Gate Voltage Drain Current IDSS mAdc

(VDS = 500 V, VGS = 0) — — 0.25
(VDS = 400 V, VGS = 0, TJ = 125°C) — — 1.0
Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF — — 100 nAdc
Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR — — 100 nAdc
ON CHARACTERISTICS*
Gate Threshold Voltage VGS(th) Vdc
(VDS = VGS, ID = 0.25 mAdc) 2.0 — 4.0
(TJ = 125°C) 1.5 — 3.5
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.5 Adc) RDS(on) — 2.4 3.0 Ohm
Drain–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 3.0 A) — — 10
(ID = 1.5 A, TJ = 100°C) — — 8.0
Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc) gFS 1.0 — — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss — 435 — pF
Output Capacitance (VDS = 25 V, VGS = 0,
Coss — 56 —
f = 1.0 MHz)
Transfer Capacitance Crss — 9.2 —
SWITCHING CHARACTERISTICS*
Turn–On Delay Time td(on) — 14 — ns
Rise Time (VDD = 250 V, ID ≈ 3.0 A, tr — 14 —
RG = 18 Ω, RL = 83 Ω,
Turn–Off Delay Time VGS(on) = 10 V) td(off) — 30 —
Fall Time tf — 20 —
Total Gate Charge Qg — 15 21 nC
(VDS = 400 V, ID = 3.0 A,
Gate–Source Charge Qgs — 2.5 —
VGS = 10 V)
Gate–Drain Charge Qgd — 10 —

SOURCE–DRAIN DIODE CHARACTERISTICS*

Forward On–Voltage (IS = 3.0 A) VSD — — 1.5 Vdc
Forward Turn–On Time ton — ** — ns
(IS = 3.0 A, di/dt = 100 A/µs)
Reverse Recovery Time trr — 200 —

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance Ld nH
(Measured from the contact screw on tab to center of die) — 3.5 —
(Measured from the drain lead 0.25″ from package to center of die) — 4.5 —
Internal Source Inductance Ls — 7.5 —
(Measured from the source lead 0.25″ from package to source bond pad)
* Indicates Pulse Test: Pulse Width = 300 µs Max, Duty Cycle ≤ 2.0%.
** Limited by circuit inductance.

2 Motorola TMOS Power MOSFET Transistor Device Data

 MTP3N50E
TYPICAL ELECTRICAL CHARACTERISTICS

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

6 1.2
TJ = 25°C
VDS = VGS
5 VGS = 10 V ID = 0.25 mA
1.1
I D, DRAIN CURRENT (AMPS)

7V
4
1
6V
3
0.9
2

0.8
1 5V
4V
0
0 2 4 6 8 10 12 14 16 18 20 –50 –25 0 25 50 75 100 125 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)

Figure 1. On–Region Characteristics Figure 2. Gate–Threshold Voltage Variation

With Temperature

VBR(DSS), DRAIN–TO–SOURCE BREAKDOWN VOLTAGE

5 1.2
VDS ≥ 10 V
VGS = 0
4 1.1
I D, DRAIN CURRENT (AMPS)

ID = 250 µA
(NORMALIZED)

3 1

2 0.9
100°C

1 0.8
25°C
TJ = –55°C
0
0 2 4 6 8 –50 0 50 100 150
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)

Figure 3. Transfer Characteristics Figure 4. Breakdown Voltage Variation

With Temperature
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

8
RDS(on) , DRAIN–TO–SOURCE RESISTANCE

VGS = 10 V 2.5
VGS = 10 V
6 ID = 1.5 A
2
(NORMALIZED)

TJ = 100°C
4 1.5

25°C 1
2

–55°C 0.5
0
0 1 2 3 4 5 –50 –25 0 25 50 75 100 125 150
ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On–Resistance versus Drain Current Figure 6. On–Resistance versus Temperature

Motorola TMOS Power MOSFET Transistor Device Data 3

MTP3N50E
SAFE OPERATING AREA INFORMATION
10 16
VGS = 20 V 1 µs
SINGLE PULSE
10 µs
TC = 25°C
I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

12
1 100 µs

1 ms
8
10 ms
0.1 dc TJ ≤ 150°C
RDS(on) LIMIT
THERMAL LIMIT 4
PACKAGE LIMIT

0.01 0
1 10 100 1000 0 100 200 300 400 500 600
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased Figure 8. Maximum Rated Switching

Safe Operating Area Safe Operating Area

FORWARD BIASED SAFE OPERATING AREA

The FBSOA curves define the maximum drain–to–source 1000
voltage and drain current that a device can safely handle VDD = 250 V td(off)
ID = 3 A
when it is forward biased, or when it is on, or being turned on.
VGS = 10 V
Because these curves include the limitations of simultaneous TJ = 25°C
high voltage and high current, up to the rating of the device, 100 td(on)
t, TIME (ns)

they are especially useful to designers of linear systems. The

curves are based on a case temperature of 25°C and a maxi-
mum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by tf
10
using the thermal response curves. Motorola Application tr
Note, AN569, “Transient Thermal Resistance–General Data
and Its Use” provides detailed instructions.

SWITCHING SAFE OPERATING AREA 1

1 10 100 1000
The switching safe operating area (SOA) of Figure 8 is the
RG, GATE RESISTANCE (OHMS)
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the Figure 9. Resistive Switching Time Variation
peak current, IDM and the breakdown voltage, V(BR)DSS. The versus Gate Resistance
switching SOA shown in Figure 8 is applicable for both turn–
on and turn–off of the devices for switching times less than
one microsecond.

1
0.7
r(t), EFFECTIVE TRANSIENT THERMAL

D = 0.5
0.5
RESISTANCE (NORMALIZED)

0.3 0.2
0.2
0.1
0.1 0.05 P(pk) RθJC(t) = r(t) RθJC
0.07 RθJC = 2.5°C/W MAX
0.05 0.02 D CURVES APPLY FOR POWER
t1 PULSE TRAIN SHOWN
0.03 0.01
t2 READ TIME AT t1
0.02 SINGLE PULSE TJ(pk) – TC = P(pk) RθJC(t)
DUTY CYCLE, D = t1/t2
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1000
t, TIME (ms)

Figure 10. Thermal Response

4 Motorola TMOS Power MOSFET Transistor Device Data

 MTP3N50E
COMMUTATING SAFE OPERATING AREA (CSOA)

The Commutating Safe Operating Area (CSOA) of 15 V

Figure 12 defines the limits of safe operation for commutated VGS
source-drain current versus re-applied drain voltage when 0
the source-drain diode has undergone forward bias. The IFM
dls/dt
curve shows the limitations of IFM and peak VR for a given 90%
commutation speed. It is applicable when waveforms similar IS
to those of Figure 11 are present. Full or half-bridge PWM DC trr
10%
motor controllers are common applications requiring CSOA
data. ton IRM
The time interval tfrr is the speed of the commutation cycle. 0.25 IRM
Device stresses increase with commutation speed, so tfrr is
specified with a minimum value. Faster commutation speeds
VDS(pk)
require an appropriate derating of IFM, peak VR or both. Ulti-
mately, tfrr is limited primarily by device, package, and circuit VR
impedances. Maximum device stress occurs during trr as the dVDS/dt
diode goes from conduction to reverse blocking. VDS
Vf VdsL
VDS(pk) is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum for-
ward source-drain diode current just prior to the onset of MAX. CSOA
commutation. STRESS AREA
VR is specified at 80% of V(BR)DSS to ensure that the Figure 11. Commutating Waveforms
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA. RGS
DUT
Stray inductances, Li in Motorola’s test circuit are assumed
to be practical minimums.
–

4 VR
+ IFM IS Li

+ VDS
I D, DRAIN CURRENT (AMPS)

3 20 V
–
VGS

2
VR = 80% OF RATED VDS
di/dt ≤ 50 A/µs VdsL = Vf + Li ⋅ dls/dt

1
Figure 13. Commutating Safe Operating Area
Test Circuit

0
0 100 200 300 400 500 600
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) V(BR)DSS
Figure 12. Commutating Safe Operating Area (CSOA) Vds(t)

IO

L
ID(t)
VDS C
4700 µF
ID
250 V

VDD
VDD

ǒ Ǔǒ Ǔ
t tP t, (TIME)
RGS
50 Ω WDSR + 1 LI 2
2 O
V(BR)DSS
V(BR)DSS – VDD

Figure 14. Unclamped Inductive Switching Figure 15. Unclamped Inductive Switching
Test Circuit Waveforms

Motorola TMOS Power MOSFET Transistor Device Data 5

MTP3N50E
1000 16

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

VDS = 100 V
TJ = 25°C 250 V
800 TJ = 25°C
VGS = 0 12 ID = 3 A
C, CAPACITANCE (pF)

600
400 V
Ciss 8
400
Crss
4
200
Coss
VDS = 0
0 0
10 5 0 5 10 15 20 25 0 5 10 15 20 25
VGS VDS QG, TOTAL GATE CHARGE (nC)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 16. Capacitance Variation Figure 17. Gate Charge versus
Gate–To–Source Voltage

+18 V VDD

1 mA
SAME
47 k 10 V 100 k DEVICE TYPE
Vin 15 V
AS DUT
2N3904 0.1 µF

2N3904
100 k
FERRITE
47 k BEAD
100 DUT

Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%

Figure 18. Gate Charge Test Circuit

6 Motorola TMOS Power MOSFET Transistor Device Data

 MTP3N50E
PACKAGE DIMENSIONS

NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
–T– PLANE Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B F C 3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
Q A A 0.570 0.620 14.48 15.75
STYLE 5: B 0.380 0.405 9.66 10.28
1 2 3 U C 0.160 0.190 4.07 4.82
PIN 1. GATE
2. DRAIN D 0.025 0.035 0.64 0.88
H F 0.142 0.147 3.61 3.73
3. SOURCE
K 4. DRAIN G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
Z J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
V J R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
G T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––
N Z ––– 0.080 ––– 2.04

CASE 221A–06
ISSUE Y

Motorola TMOS Power MOSFET Transistor Device Data 7

MTP3N50E

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*MTP3N50E/D*
8 ◊ Motorola TMOS Power MOSFET Transistor Device Data
MTP3N50E/D