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PLC 2-Bit Magnitude Comparator Program

The document describes a PLC program to implement a 2-bit magnitude comparator. It involves writing the truth table and Karnaugh maps for the outputs A<B, A=B, and A>B based on the 2-bit inputs A1, A0, B1, and B0. The PLC ladder logic program realizes the logic expressions using contacts and coils to output the comparison of the 2-bit input values. The program is tested with example input cases and verifies the correct output comparison.

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Maria Guerrero
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278 views5 pages

PLC 2-Bit Magnitude Comparator Program

The document describes a PLC program to implement a 2-bit magnitude comparator. It involves writing the truth table and Karnaugh maps for the outputs A<B, A=B, and A>B based on the 2-bit inputs A1, A0, B1, and B0. The PLC ladder logic program realizes the logic expressions using contacts and coils to output the comparison of the 2-bit input values. The program is tested with example input cases and verifies the correct output comparison.

Uploaded by

Maria Guerrero
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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PLC Program to Implement 2-bit Magnitude

Comparator
This is a PLC Program to Implement 2-bit Magnitude Comparator.

Problem Description
Implementing 2-bit comparator in PLC using Ladder Diagram programming
language.

Problem Solution
 For a 2-bit comparator, each input word is 2 bit long.
 Writing truth table showing the comparison of input words.
 For each output AB, write Karnaugh-Map.
 From the K-Map, obtaining a simplified expression for each output in terms of 2-bit
inputs.
 Realize the code converter using the Logic Gates.

By comparing both word inputs, Truth Table can be written as given


below.
Decimals Inputs Outputs
A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 0 0 1 0
1 0 0 0 1 1 0 0
2 0 0 1 1 1 0 0
3 0 0 1 0 1 0 0
4 0 1 1 0 0 0 1
5 0 1 1 1 0 1 0
6 0 1 0 1 1 0 0
7 0 1 0 0 1 0 0
8 1 1 0 0 0 0 1
9 1 1 0 1 0 0 1
10 1 1 1 1 0 1 0
11 1 1 1 0 1 0 0
12 1 0 1 0 0 0 1
13 1 0 1 1 0 0 1
14 1 0 0 1 0 0 1
15 1 0 0 0 0 1 0

Boolean expression for each output bit can be written as


A<B = m(1, 2, 3, 6, 7, 11)
A=B = m(0, 5, 10, 15)
A>B = m(4, 8, 9, 12, 13, 14)
Karnaugh-Map for each output
Realizing code conversion using Logic Gates

PLC Program
Here is PLC program to Implement 2-bit Magnitude Comparator, along with
program explanation and run time test cases.
List of Inputs and Outputs
A1 = I:1/0 (Input)
A0 = I:1/1 (Input)
B1 = I:1/2 (Input)
B0 = I:1/3 (Input)
A<B = O:2/0 (Output)
A=B = O:2/1 (Output)
A>B = O:2/2 (Output)

Ladder Diagram to obtain Binary output

Program Description
 RUNG000 is used to detect if A is less than B. first compares A1 and B1 bits. If A1
is less than B1 then O:2/0 is set otherwise it similarly compares A0 and B0.
 RUNG001 is used to detect the condition when A=B are equal. ANDing of two EX-
NOR gates ae obtained by simplifying expression using De-Morgan’s Theorem.
 O:2/1 is set only when A1A0=B1B0.
 RUNG002 works similarly as RUNG000, it first compares A1 and B1, if A1 is
greater than B1 then output O:2/2 is set to 1 and if not, it compares A0 and B0.
Runtime Test Cases
Decimals Inputs Outputs
A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 0 0 1 0
1 0 0 0 1 1 0 0
2 0 0 1 1 1 0 0
3 0 0 1 0 1 0 0
4 0 1 1 0 0 0 1
5 0 1 1 1 0 1 0
6 0 1 0 1 1 0 0
7 0 1 0 0 1 0 0
8 1 1 0 0 0 0 1
9 1 1 0 1 0 0 1
10 1 1 1 1 0 1 0
11 1 1 1 0 1 0 0
12 1 0 1 0 0 0 1
13 1 0 1 1 0 0 1
14 1 0 0 1 0 0 1
15 1 0 0 0 0 1 0

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