Microcontrollers
Section #1
Spring 23-24
Problem 1 Find the organization and capacity of memory chips with the
following pins.
a. EEPROM A0–A14, D0–D7
b. SRAM A0–A12, D0
c. DRAM A0–A8, D0–D3
1
Problem 1 Find the organization and capacity of memory chips with the
following pins.
a. EEPROM A0–A14, D0–D7
b. SRAM A0–A12, D0
c. DRAM A0–A8, D0–D3
Solution
A0 D0
a. 32K x 8, 256K A1
A2 D1
A3
• Address Pins (A0–A14): 15 address pins. A4 D2
A5
• Data Pins (D0–D7): 8 data pins. A6 D3
A7
• Organization: This EEPROM chip has 32,768 locations (2^15 = 32,768), A8 D4
A9
and each location can store 8 bits of data. Therefore, it is often A10
A11
D5
A12 D6
represented as 32Kx8. A13
A14 D7
2
Problem 1 Find the organization and capacity of memory chips with the
following pins.
a. EEPROM A0–A14, D0–D7
b. SRAM A0–A12, D0
c. DRAM A0–A8, D0–D3
Solution
A0 D0
b. 8Kx1, 8K A1
A2
A3
A4
• Address Pins (A0–A12): 13 address pins. A5
A6
A7
• Data Pin (D0): 1 data pin. A8
A9
A10
• Organization: The SRAM chip has 8,192 locations (2^13 = 8,192), and A11
A12
each location stores 1 bit of data. It is typically represented as 8Kx1
3
Problem 1 Find the organization and capacity of memory chips with the
following pins.
a. EEPROM A0–A14, D0–D7
b. SRAM A0–A12, D0
c. DRAM A0–A8, D0–D3
Solution
A0 D0
c. 512 x 4, 2K A1
A2 D1
Address Pins (A0–A8): 9 address pins.
A3
• A4 D2
A5
• Data Pins (D0–D3): 4 data pins. A6 D3
A7
• Organization: This DRAM chip has 512 locations (2^9 = 512), and each A8
location can hold 4 bits of data. It can be denoted as 512x4
4
Problem 2 Find the capacity, address, and data pins for the following
memory organizations.
a. 1M × 8 SRAM
b. 4M × 4 DRAM
5
Problem 2 Find the capacity, address, and data pins for the following
memory organizations.
a. 1M × 8 SRAM
b. 4M × 4 DRAM
Solution
a. Capacity = 1 MB , Addresses = 20 , Data pins = 8
• Capacity: 1M × 8 refers to 1 Megabit (1M) of memory with each location storing 8 bits (or 1 byte) of data.
• 1 Megabit = 1,048,576 bits
• 1 byte = 8 bits
• Therefore, the total capacity is 1,048,576 bytes or approximately 1 Megabyte.
• Address pins: Since there are 1M memory locations, we need enough address pins to address each location. The
number of address pins required can be calculated using log2(1M) = log2(2^20) = 20 address pins.
• Data pins: The memory stores 8 bits (1 byte) of data per location, so there are 8 data pins.
6
Problem 2 Find the capacity, address, and data pins for the following
memory organizations.
a. 1M × 8 SRAM
b. 4M × 4 DRAM
Solution
b. Capacity = 2 MB , Addresses = 22 , Data pins = 4
• Capacity: 4M × 4 refers to 4 Megabit (4M) of memory with each location storing 4 bits (or 0.5 byte) of data.
• 4 Megabit = 4*1,048,576 = 4194304 bits
• 0.5 byte = 4 bits
• Therefore, the total capacity is 2,097,152 bytes or approximately 2 Megabyte.
• Address pins: Since there are 4M memory locations, we need enough address pins to address each location. The
number of address pins required can be calculated using log2(4M) = log2(2^22) = 22 address pins.
• Data pins: The memory stores 4 bits (0.5 byte) of data per location, so there are 4 data pins.
7
Problem 3 Find the address range of the memory design in the diagram.
8
Problem 3 Find the address range of the memory design in the diagram.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
To select chip A15 - A14 must be 01
so address range
from 0100 0000 0000 0000 = 0x4000 H
To 0111 1111 1111 1111 = 0x7FFF H
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
From 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
To 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
