Source:Digital

Integrated Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić

VLSI Design-R-19-Unit-4-Part-1
CMOS Combinational Logic Circuit
Design

1
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Combinational vs. Sequential Logic

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

2
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

3
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Static Complementary CMOS
VDD

In1
PMOS only
In2 PUN
InN
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN

PUN and PDN are dual logic networks

4
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

5
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

6
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Complementary CMOS Logic Style

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© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Example Gate: NAND

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© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Example Gate: NOR

9
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

10
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Constructing a Complex Gate
VDD VDD

C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

11
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 CMOS Properties( or advantages)
 Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state;
low output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power
and ground; no static power dissipation
 Propagation delay is function of load
capacitance and resistance of transistors
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© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Ratioed Logic

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© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Ratioed Logic

VDD VDD VDD

Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

14
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Ratioed Logic
VDD

• N transistors + Load
Resistive
Load • VOH = V DD
RL

• VOL = RPN
F RPN + RL

In1 • Assymetrical response

In2 PDN
In3 • Static power consumption

• tpL= 0.69 RLCL

VSS

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© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Active Loads
VDD VDD

Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3

VSS VSS

depletion load NMOS pseudo-NMOS

16
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Pseudo-NMOS

VDD

F
CL
A B C D

VOH = VDD (similar to complementary CMOS)

 V2  k 2
k  V – V V OL p V
n DD Tn OL
– -------------  = ------  DD
– V
Tp 
 2  2

kp
V OL =  VDD – V T  1 – 1 – ------ (assuming that V T = V Tn = VTp )
kn

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

17
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Improved Loads
VDD VDD

M1 M2

Out Out

A
A PDN1 PDN2
B
B

VSS VSS

Differential Cascode Voltage Switch Logic (DCVSL)

18
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
DCVSL Example

Out

Out

B B B B

A A

XOR-NXOR gate
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© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Pass-Transistor
Logic

20
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Pass-Transistor Logic

Switch Out A
Out
Inputs

Network B
B

• N transistors
• No static consumption

21
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Example: AND Gate

A
B
F = AB

22
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Transmission Gate
C
C

A B A B

C
C

C = 2.5 V
A = 2.5 V
B
CL
C=0V

23
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Pass-Transistor Based Multiplexer

V DD
S

A
M2

S F

M1
B

24
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Dynamic Logic

25
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Dynamic CMOS
 In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
 fan-in of n requires 2n (n N-type + n P-type)
devices

 Dynamic circuits rely on the temporary

storage of signal values on the capacitance of
high impedance nodes.
 requires on n + 2 (n+1 N-type + 1 P-type)
transistors
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© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Dynamic CMOS logic-basic principles

off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)
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© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Conditions on Output
 Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
 Inputs to the gate can make at most one
transition during evaluation.

 Output can be in the high impedance state

during and after evaluation (PDN off), state is
stored on CL

29
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Properties (Advantages) of Dynamic Gates

 Logic function is implemented by the PDN only

 number of transistors is N + 2 (versus 2N for static complementary
CMOS) so LOW AREA.
 Full swing outputs (VOL = GND and VOH = VDD)
 Non-ratioed - sizing of the devices does not affect
the logic levels
 Faster switching speeds
 reduced load capacitance due to lower input capacitance (Cin)
 reduced load capacitance due to smaller output loading (Cout)
 no Isc, so all the current provided by PDN goes into discharging CL

30
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Properties (Disadvantages) of Dynamic Gates

 Overall power dissipation usually higher than static

CMOS
 no static current path ever exists between VDD and GND
(including Psc)
 no glitching
 higher transition probabilities
 extra load on Clk
 PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
 low noise margin (NML)
 Needs a precharge/evaluate clock
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© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Speed and power dissipation of Dynamic Logic

 Overall power dissipation of dynamic CMOS logic

is usually higher than static CMOS
 no static current path ever exists between VDD and GND
(including Psc)
 no glitching power
 higher transition probabilities, so high power dissipation
 extra load on Clk signal, so high power dissipation
 Faster switching speeds
 reduced load capacitance due to lower input capacitance (Cin)
 reduced load capacitance due to smaller output loading (Cout)
 no Isc, so all the current provided by PDN goes into discharging CL

32
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Speed and power dissipation of Dynamic Logic

 Low load capacitance CL

 Propagation delay from low to high transition
tPLH=0
 Propagation delay from high to low transition
tPHL α CL
 tPHL α current sinking capabilities of PDN
 Evaluation transistor (Me) slowes down speed.
 If we remove Evaluation transistor (Me) speed
increases but static power disssipation
increases.
33
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Issues in Dynamic Design 1:
Charge Leakage
CLK
Clk Mp
Out

A CL

VOut Evaluate
Clk Me
Precharge

Leakage sources

Dominant component is subthreshold current

34
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Solution to Charge Leakage
Keeper transistor

Clk Mp Mkp

A Out
CL
B

Clk Me

Use keeper transistor to remove charge leakage as

shown.

35
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Issues in Dynamic Design 2:
Charge Sharing or redistribution

Charge stored originally on

Clk Mp CL is redistributed (shared)
Out over CL and CA leading to
A CL reduced robustness
B=0 CA

Clk Me CB

36
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Solution to Charge Sharing or redistribution

Clk Mp Mkp Clk

Out
A

Clk Me

Precharge internal nodes using a clock-driven transistor

(at the cost of increased area and power)

37
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Issues in Dynamic Design 3:
Backgate Coupling

Clk Mp Out1 =1
Out2 =0
A=0 In
CL1 CL2

B=0

Clk Me

Dynamic NAND Static NAND

38
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Issues in Dynamic Design 4: Clock
Feedthrough

Coupling between Out and

Clk Mp Clk input of the precharge
Out device due to the gate to
A CL drain capacitance. So
voltage of Out can rise
B
above VDD. The fast rising
Clk Me (and falling edges) of the
clock couple to Out.

39
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Clock Feedthrough
Clock feedthrough
Clk
Out 2.5
In1
In2 1.5

In3 In &
0.5 Clk
In4 Out
Clk -0.5
0 0.5 Time, ns 1
Clock feedthrough

40
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Other Effects

 Capacitive coupling
 Substrate coupling
 Minority charge injection
 Supply noise (ground bounce)

41
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Cascading Dynamic Gates
V

Clk Clk Clk

Mp Mp
Out2
Out1
In
In

Clk Clk VTn

Me Me Out1

V
Out2

Only 0  1 transitions allowed at inputs!

42
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Cascading Dynamic Gates

43
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Domino Logic

Clk Mp Clk Mp Mkp

11
Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

44
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Properties of Domino Logic

 Only non-inverting logic can be implemented

 Very high speed
 static inverter can be skewed, only L-H transition
 Input capacitance reduced – smaller logical effort

45
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Choosing a Logic style

46
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Choosing a Logic style

47
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Gate design in the Ultra Deep-Submicron
Era(Nanometer Technology)
 Ultra deep submicron means latest nanometer technology
such as 22 nm, 7 nm, 4 nm etc.
 Reason for going to Ultra deep submicron technology is to
increase packaging density and fabricate very small area
chips and devices(miniaturization).
 In Ultra deep submicron technology channel length is very
very small, and we call it as Short channel.
 Also we use lower supply voltages and threshold voltages to
minimize Power dissipation.
 Subthreshold leakage current is a very serious issue in Short
channel MOS transistors in Ultra deep submicron era.
 Gate design in the Ultra deep submicron technology needs
to consider the following short channel effects :

48
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Gate design in the Ultra Deep-Submicron
Era(Nanometer Technology)
 1.Velocity saturation
 2.Channel depletion region charge reduction
 3.Drain Induced Barrier lowering(DIBL)
 4.Punch-through effect
 5.Hot electron effects
 6.Narrow channel effect
 7.Thinning of oxide layer thickness(tox)
 So due to above short channel effects large subthreshold
leakage current results.
 So Gate design in ultra deep submicron era have to address
the above short channel effects and special designs are
needed to minimize leakage current and increase speed.

49
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Source:Digital
Integrated Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

VLSI Design-R19-Unit-4-Part-2
CMOS Sequential Logic Circuit
Design

© Digital Integrated Circuits2nd

Sequential Circuits
 Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC

Current State
Next state
Registers
Q D

CLK

2 storage(Memory) mechanisms
• positive feedback
• charge-based

© Digital Integrated Circuits2nd

Sequential Circuits
 Naming Conventions

 Here
 a latch is level sensitive
 a register is edge-triggered

© Digital Integrated Circuits2nd

Sequential Circuits
 Latch versus Register
 Register stores data when clock
 Latch stores data when clock is at low rises(0-to-1) or falls(1-to-0). Register
level (Negative latch) or at high level is edge-triggered. Edge-triggered
(Positive latch). Latch is a level-sensitive registers only sample the input on a
circuit that passes the D input to the Q clock transition — 0-to-1 for a positive
output when the clock signal is at low or edge-triggered register, and 1-to-0 for
high level. a negative edge-triggered register.

D Q D Q

Clk Clk

Clk Clk

D D

Q Q

© Digital Integrated Circuits2nd

Sequential Circuits
 Latches

A Positive latch passes the D input to the Q A negative latch passes the D input to
output(transparent) when the clock signal is high. the Q output (transparent) when the
clock signal is low.
© Digital Integrated Circuits2nd
Sequential Circuits
 Latch-Based Design
In this the design of the sequential circuits such as Registers, counters
etc. involve Negative latch and Positive latches as shown in fig.

• N latch is transparent • P latch is transparent

when f = 0(Clock) when f = 1(Clock)
f

N P
Logic
Latch Latch

Logic

© Digital Integrated Circuits2nd

Sequential Circuits
 Timing Definitions, Setup time, Hold time, Propagation delay
•There are three important timing parameters associated with a register
as illustrated in Figure.
•The set-up time (tsu) is the time that the data inputs (D input) must be valid before the
clock transition (this is, the 0 to 1 transition for a positive edge-triggered register).
•The hold time (thold) is the time the data input must remain valid after the clock edge.

CLK
t Register
tsu thold D Q

D DATA CLK
STABLE t
tc 2 q
Fig.Timing definitions of a
Q DATA
Synchronous register
STABLE t

Assuming that the set-up and hold-times are met, the data at the D input is copied
to the Q output after a worst-case propagation delay (with reference to the clock
edge) denoted by tc-q.

© Digital Integrated Circuits2nd

Sequential Circuits
 Timing Definitions, Setup time, Hold time, Propagation
delay
Assume that the worst-case propagation delay of the
logic equals tplogic, while its minimum delay (also called
the contamination delay) is tc-d. The minimum clock
period T (or maximum clock frequency fclk), required for
proper operation of the sequential circuit is given by
T ≥ tc-q + t plogic + tsu
The hold time of the register imposes an extra
constraint for proper operation,

tcdregister + tcdlogic ≥ thold

where tcdregister is the minimum propagation delay (or

contamination delay) of the register.
© Digital Integrated Circuits2nd
Sequential Circuits
 Positive Feedback: Bi-Stability

© Digital Integrated Circuits2nd

Sequential Circuits
 Positive Feedback: Bi-Stability

© Digital Integrated Circuits2nd

Sequential Circuits
 Positive Feedback: Bi-Stability

© Digital Integrated Circuits2nd

Sequential Circuits
 Instability and/or Metastability

Meta-Stability : Gain
should be larger
than 1 in the
transition region

© Digital Integrated Circuits2nd

Sequential Circuits
 Cross coupled NOR –based SRFF (or register)

© Digital Integrated Circuits2nd

Sequential Circuits
 Cross coupled NAND –based SRFF (or register)

© Digital Integrated Circuits2nd

Sequential Circuits
 Cross coupled NAND –based SRFF (or register)

© Digital Integrated Circuits2nd

Sequential Circuits
 Clocked CMOS register(SRFF)

© Digital Integrated Circuits2nd

Sequential Circuits
 Clocked CMOS register(SRFF)

© Digital Integrated Circuits2nd

Sequential Circuits
 JK-FlipFlop

© Digital Integrated Circuits2nd

Sequential Circuits
 T -FF and D -FF

© Digital Integrated Circuits2nd

Sequential Circuits
 Race around condition

© Digital Integrated Circuits2nd

Sequential Circuits
 SR Master –Slave Register

© Digital Integrated Circuits2nd

Sequential Circuits
 SR Master –Slave Register

© Digital Integrated Circuits2nd

Sequential Circuits
 Multiplexer-Based Latches

© Digital Integrated Circuits2nd

Sequential Circuits
 Multiplexer-Based Latches

© Digital Integrated Circuits2nd

Sequential Circuits
 Multiplexer-Based Latches

© Digital Integrated Circuits2nd

Sequential Circuits
 Multiplexer-Based Latches

© Digital Integrated Circuits2nd

Sequential Circuits
 Master-Slave Based Edge Triggered Register

© Digital Integrated Circuits2nd

Sequential Circuits
 Master-Slave Based Edge Triggered Register

Two opposite latches trigger on edge

Also called master-slave latch pair
© Digital Integrated Circuits2nd
Sequential Circuits
 Master-Slave Based Edge Triggered Register

Multiplexer-
based latch pair
© Digital Integrated Circuits2nd
Sequential Circuits
 Timing Properties of Multiplexer-based Master-Slave Registers

© Digital Integrated Circuits2nd

Sequential Circuits
 Timing Properties of Multiplexer-based Master-Slave Registers
1.Setup Time:

© Digital Integrated Circuits2nd

Sequential Circuits
 Timing Properties of Multiplexer-based Master-Slave Registers

2.Hold Time:

© Digital Integrated Circuits2nd

Sequential Circuits
 Timing Properties of Multiplexer-based Master-Slave Registers
3.Clock to q Delay(Propagation delay)

© Digital Integrated Circuits2nd

Sequential Circuits
 Reduced Clock Load Master-Slave Register

© Digital Integrated Circuits2nd

Sequential Circuits
 Reduced Clock Load Master-Slave Register

© Digital Integrated Circuits2nd

Sequential Circuits
 Reduced Clock Load Master-Slave Register

© Digital Integrated Circuits2nd

Sequential Circuits
 Avoiding Clock Overlap-
CLK X CLK
Q
A
D
B

CLK CLK
(a) Schematic diagram

CLK

CLK
(b) Overlapping clock pairs
Fig.(a).Master-slave register based on NMOS-only pass transistors.

© Digital Integrated Circuits2nd

Sequential Circuits
 Storage Mechanisms

© Digital Integrated Circuits2nd

Sequential Circuits
 Storage Mechanisms

Static(Positive feedback) Dynamic (charge-based)

CLK
CLK

D Q
Q

CLK
CLK
D

CLK

© Digital Integrated Circuits2nd

Sequential Circuits
 PIPELINING

© Digital Integrated Circuits2nd

Sequential Circuits
 PIPELINING

© Digital Integrated Circuits2nd

Sequential Circuits
 PIPELINING

© Digital Integrated Circuits2nd

Sequential Circuits
 PIPELINING

© Digital Integrated Circuits2nd

Sequential Circuits