Total No. of Questions : 8] SEAT No.
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P1486 [Total No. of Pages : 2
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S.E. (Electronics/Electronics & Computer/E & TC)
8s
DIGITAL CIRCUITS
1:1
(2019 Pattern) (Semester - III) (204182)
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Time : 2½Hours] [Max. Marks : 70
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Instructions to the candidates:
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1) Answer [Link].1 or [Link].2, [Link].3 or [Link].4, [Link].5 or [Link].6, [Link].7 or [Link].8.
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2) Neat diagrams must be drwan wherever necessary.
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3) Figures to the right indicates full marks.
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Q1) a) Explain the working of a half-adder? Draw its logic diagram. [7]
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b) Implement the full subtractor using a 1 : 8 demultiplexer. [5]
c) Implement the following function using multiplexer
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f (A,B,C) = ∑m (0, 2, 4, 6). [5]
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Q2) a) Draw the logic diagram of full-adder and its truth table. [7]
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b) Implement a full-adder using Demultiplexer. [5]
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c) Implement the given logic function using a 4 : 1 multiplexer.
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f (A,B,C) = ∑m (0, 2, 4, 6). [5]
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Q3) a) For the state diagram shown in figure, obtain the state table and design
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the circuit using minimum number of J = K flip - flops. [8]
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b) Explain the function of a shift register. Give its application. [5]
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c) Explain with truth table the working of clocked RS flip-flop. [5]
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Design a sequence generator using T FFs 0 → 1 → 7 → 4 → 2 .
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Q4) a) [8]
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b) Explain the types of shift register. [5]
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c) Explain with diagram the working of D type Flip-flop. Give its truth table.[5]
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P.T.O.
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Q5) a) Design the clocked sequential circuit for the state diagram using JK flip
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flop. [9]
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b) Draw ASM chart for a 2 bit up-down counter having mode control input
M. [8]
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M=1 Up counter.
M = 0 Down Center.
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Q6) a) Design a sequential circuit using Mealy machine for detecting the
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sequence......1001.......Use Jk Flip-flop. [9]
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b) Explain in short: [8]
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i) State Diagram.
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ii) ASM chart.
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Q7) a) Explain the classification of memories based on their principle of
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operation. [8]
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b) Write a short note on concept of PLA and PAL. [10]
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Q8) a) Explain with circuit diagram the dynamic MOS memory. [8]
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b) A combinational circuit defined by the function. [10]
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F1(A, B, C) = ∑ (3, 5, 6, 7) and F2(A, B, C) = ∑ (0, 2, 4, 7)
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Implement the circuit with PLA having 3 inputs, 3 products terms and 2
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out puts.
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