National University of Computer & Emerging Sciences, Lahore
Department of Electrical Engineering (Fall 2024)
EE1005 – Digital Logic Design (BCS-3A)
Assignment#1
Due Date:
Question#1: CLO-01
Convert the following numbers from the given base to the other three bases listed in the table:
Decimal Binary Octal Hexadecimal
251.6875
11011011.1011
743.52
3F4.8
Question#2: CLO-02
A) Simplify the following Boolean expression using algebric manipulation:
𝐹1 = [𝐴𝐵(𝐶 + 𝐵𝐷) + 𝐴𝐵]𝐶
𝐹2 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶
𝐹3 = (𝐴𝐵 + 𝐴𝐶) + 𝐴𝐵𝐶
B) Draw logic diagram for the simplified Boolean functions.
C) Find level of implementation of each logic circuit drawn in part (B).
Question#3: CLO-02
Prove the equality of the following Boolean expressions:
a) 𝐴𝐵 + 𝐵𝐶𝐷 + 𝐴𝐵𝐶 + 𝐶𝐷 = 𝐵 + 𝐶𝐷
b) 𝑊𝑌 + 𝑊𝑌𝑍 + 𝑊𝑋𝑍 + 𝑊𝑋𝑌 = 𝑊𝑌 + 𝑊𝑋𝑍 + 𝑋𝑌𝑍 + 𝑋𝑌𝑍
c) 𝐴𝐶 + 𝐴𝐵 + 𝐵𝐶 + 𝐷 = (𝐴 + 𝐵 + 𝐶 + 𝐷)(𝐴 + 𝐵 + 𝐶 + 𝐷)
Question#4: CLO-02
Optimize the following expressions in (1) SOP and (2) POS:
a) 𝐴𝐶 + 𝐵𝐷 + 𝐴𝐶𝐷 + 𝐴𝐵𝐶𝐷
b) (𝐴 + 𝐵 + 𝐷)(𝐴 + 𝐵 + 𝐶)(𝐴 + 𝐵 + 𝐷)(𝐵 + 𝐶 + 𝐷)
National University of Computer & Emerging Sciences, Lahore
Department of Electrical Engineering (Fall 2024)
c) (𝐴 + 𝐵 + 𝐷)(𝐴 + 𝐷)(𝐴 + 𝐵 + 𝐷)(𝐴 + 𝐵 + 𝐶 + 𝐷)
Question#5: CLO-02
Use Karnaugh map to find both minimal SOP and POS expressions for the following Boolean
functions:
a) 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(2, 3, 5, 7, 8, 10, 12, 13)
b) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∏ 𝑀(5, 12, 13, 14)
c) 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(5, 6, 11, 12) , 𝑑(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(0, 1, 2, 9, 10, 14, 15)
d) 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∏ 𝑀(3, 4, 6, 11, 12, 14), 𝑑(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(0, 1, 2, 7, 8, 9, 10)
Question#6: CLO-02
Four chairs are placed in a row:
The row may be occupied (“1”) or empty (“0”). Write a logic function F(A, B, C, D) which is 1 if and only if
there are no adjacent empty chairs. Design a Digital Circuit implementing this function using AND, OR,
NOT gates.
Question#7: CLO-02
You are required to design a digital circuit that takes two numbers ‘m’ (2 bit) and ‘n’ (2 bit) as
input and checks that whether the applied input satisfies the following inequality equation or not.
4𝑚 + 𝑛 + 4≥10
Show all necessary steps to design the required system optimally, from truth table to circuit
diagram.
National University of Computer & Emerging Sciences, Lahore
Department of Electrical Engineering (Fall 2024)
Question#8: For the logic circuit given in the figure below do the following: CLO-02
a) Implement the following optimized function with NOR gates ONLY. Complements of
inputs are not directly available.
𝐹(𝐴, 𝐵, 𝐶, 𝐷, 𝐸) = 𝐴𝐵𝐶 + 𝐷𝐸
b) Redraw the circuit using NAND gates only.
Design a combinational circuit
with three inputs x, y and z and
three outputs A, B and C. When
National University of Computer & Emerging Sciences, Lahore
Department of Electrical Engineering (Fall 2024)
the binary input is 0, 1, 2 or 3,
the binary output is two greater
than the input. When the binary
input is 4, 5, 6 or 7, the binary
output is three lesser the input.
Design a combinational circuit
with three inputs x, y and z and
three outputs A, B and C. When
the binary input is 0, 1, 2 or 3,
the binary output is two greater
than the input. When the binary
input is 4, 5, 6 or 7, the binary
output is three lesser the input.
National University of Computer & Emerging Sciences, Lahore
Department of Electrical Engineering (Fall 2024)
Design a combinational circuit
with three inputs x, y and z and
three outputs A, B and C. When
the binary input is 0, 1, 2 or 3,
the binary output is two greater
than the input. When the binary
input is 4, 5, 6 or 7, the binary
output is three lesser the input.
Question#9: CLO-02
Design a combinational circuit with three inputs p, q, and r and three outputs X, Y, and Z. The
circuit should function as follows:
● When the binary input (p, q, r) is 0, 1, 2, or 3, the binary output is four greater than the
input.
● When the binary input is 4 or 5, the binary output is equal to the input.
● When the binary input is 6 or 7, the binary output is three less than the input.
Show all necessary steps to design the required system, including the truth table, Karnaugh map
simplification, and the circuit diagram.
National University of Computer & Emerging Sciences, Lahore
Department of Electrical Engineering (Fall 2024)
Question#10: CLO-02
A warehouse needs a warning light to indicate when it is time to perform a scheduled safety
check. The warning light should be activated under the following conditions:
1. It's between 3 PM and 4 PM, and all employees are present in the warehouse.
2. It's Monday, and the temperature in the warehouse exceeds the safety threshold,
regardless of employee presence.
3. It's the end of the month, the warehouse is operating at full capacity, and the temperature
is close to the safety threshold.
Design a logic circuit that will control the warning light. (Hint: Use five logic input variables to
represent the various conditions.)
Example: An input T will be HIGH only when the time of day is between 3 PM and 4 PM.
