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MOS Transistor Operation Explained

The document describes the operation of MOS transistors. 1) MOS transistors have four terminals - gate, source, drain, and substrate. Applying a gate voltage above the threshold voltage creates an inversion layer channel between source and drain. 2) In the linear region, for small drain voltages a current flows proportionally to the drain voltage. At the pinch-off point, the maximum drain voltage is reached. 3) Beyond pinch-off, in saturation region, the channel is pinched off near the drain and the current becomes independent of the drain voltage.

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Concetto Cantone
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173 views10 pages

MOS Transistor Operation Explained

The document describes the operation of MOS transistors. 1) MOS transistors have four terminals - gate, source, drain, and substrate. Applying a gate voltage above the threshold voltage creates an inversion layer channel between source and drain. 2) In the linear region, for small drain voltages a current flows proportionally to the drain voltage. At the pinch-off point, the maximum drain voltage is reached. 3) Beyond pinch-off, in saturation region, the channel is pinched off near the drain and the current becomes independent of the drain voltage.

Uploaded by

Concetto Cantone
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MOS Transistor Operation

Gate S/D Channel width (W) Oxide n+ Channel Length (L) Substrate (p-Si) n+ S/D

MOS is four-terminal device if the fourth terminal is not shown it is assumed to be connected to the appropriated voltage (lowest and highest supply voltage value for NMOS and PMOS, respectively)
Prof. Gaetano Palumbo 1

VG < V to

V >V to G

Oxide n+
Depletion region

Oxide n+ n+ p n+ Inversion layer (channel)

Substrate region (p)

The diffusion junction are reverse-biased (to achieve this condition the bulk voltage must in NMOS be always lower than the other node voltages) A gate voltage greater than the Threshold Voltage, Vto, is needed to create a surface inversion The depth of the inversion layer is independent from gate voltage
Prof. Gaetano Palumbo 2

VG > Vto VS = 0 Oxide Source n+ p

0 < VD < VDSsat ID

Drain n+

When the inversion layer is established an n-type conduction channel between source and drain is formed For small drain voltage a current proportional to drain voltage flows in the channel: linear behavior (linear or triode region) in the linear region the MOS acts like a voltage-controlled resistor (the control input is the gate node)

Prof. Gaetano Palumbo

VG > Vto VS = 0 Oxide Source n+ p Pinch-off point

VD = VDSsat ID Drain n+

The linear region holds until the drain voltage reaches the VDSsat value Under this condition the inversion layer at the drain is reduced to zero: Pinch-off point This condition is the border between the linear and the saturation region

Prof. Gaetano Palumbo

VG > Vto V =0 S Oxide Source n+ p


Pinch-off point

VD > VDSsat ID

Drain n+

Beyond the pinch-off point (VD>VDSsat) a depleted surface region forms adjacent to the drain: Saturation region The depleted surface grows toward the source with increasing drain voltage the effective channel length is reduced

Prof. Gaetano Palumbo

VG > Vto V =0 S Oxide Source n+ p


Pinch-off point

VD > VDSsat ID

Drain n+

The pinched-off (depleted) section absorbs most of the excess voltage drop VDS-VDSsat. Electrons arriving from the source through the channel are injected into the drain-depletion region and are accelerated toward the drain in this high electric field

Prof. Gaetano Palumbo

MOS Threshold Voltage


It is due to 4 physical component 1) the work function difference between the gate and the channel (built-in potential of the MOS structure) 2) the voltage needed to change the surface potential 3) the voltage to offset the depletion region charge 4) the voltage to offset the fixed charge in the silico-oxide interface (and in the gate oxide)

Q Q Vt = ms 2F B ox Cox Cox
Prof. Gaetano Palumbo 7

The Flat-Band voltage,VFB,is the built-in offset across the MOS structure, it is

Q VFB =ms ox Cox

Q Vt = VFB 2F B Cox

VFB, F and Cox (=ox/tox) are technology parameters QB depends on the source-bulk voltage
QB = 2qNAsi 2F +VSB

Prof. Gaetano Palumbo

Vt =Vto + 2F +VSB 2F

Vto, is the threshold voltage for VBS=0


QB0 = 2qNAsi 2F

Q Vto = VFB 2F B0 Cox 2qsiN A Cox

is the body-effect coefficient

Prof. Gaetano Palumbo

MOS Current-Voltage characteristic


Use of the gradual channel approximation reduce the analysis to a one-dimensional current-flow problem the approximation is heavy for small-geometry MOS
VG > Vto VS = 0 Oxide Source n+ p Drain n+ 0 < VD < VDSsat ID

x y=0

y y=L

Prof. Gaetano Palumbo

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Assume the threshold voltage, Vto, constant along the channel from y=0 to y=L (this is an approximation since the channel voltage is not constant) Assume the electric field component, Ey, along the ycoordinate is dominant compared to the one along the xcoordinate, Ex (allows to reduce the current flow only to the ydimesion) The channel voltage, VC(y),with respect to the bulk is: VC(0)=0 and VC(L)= VD

Prof. Gaetano Palumbo

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The total mobile electron charge in the surface inversion layer, QI(y), is
QI ( y ) = Cox [VG Vc ( y ) Vto ]
y=0 Channel length = L y=L Channel width = W

dy Source end Inversion layer (channel)

Drain end

Assuming all mobile electrons with a constant surface mobility, n, the incremental resistance, dR, is (the minus sign is for
the negative polarity of QI(y))

dR =

dy W n QI ( y )
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Prof. Gaetano Palumbo

Applying Ohms law along y-direction and then integrating from 0 to L


dVc = I D dR = ID dy W n QI ( y )
L 0 VDS 0

I D dy = W n

QI ( y) dVc

I D L = W n COX

VDS 0

(VG Vc Vto ) dVc

C W 2 I D = n ox [ 2 (VG Vto )VDS VDS ] 2 L


Prof. Gaetano Palumbo

Linear region
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The current voltage curves are inverted parabolas for each constant VG The peak of the parabolas is at VDS = VG-Vto . Pinch-off occurs The theoretical behavior of the drain current is decreasing after the peak, but it is unrealistic and the current is ideally constant

For VDS > VG-Vto = VDSsat


C W I D = n ox (VG Vto ) 2 2 L
Prof. Gaetano Palumbo

Saturation region

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C W 2 I D = n ox [ 2 (VGS Vt )VDS VDS ] L 2 C W I D = n ox (VGS Vt ) 2 2 L


ID VD VG VB VS ID VG ID V D VS VG VB VS V D

Linear region

Saturation region

Depletion Vto<0
VG

ID VD VB VS

n, Cox are technological parameter, Vt is both technological and electrical parameter W/L is the design parameter
Prof. Gaetano Palumbo

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PMOS Current-Voltage characteristic


ID = p Cox W 2 [ 2 (VSG + Vt )VSD VSD ] = 2 L C W 2 = p ox [ 2 ( VGS Vt ) VDS VDS ] 2 L p Cox W (VSG + Vt ) 2 = 2 L p Cox W = ( VGS Vt ) 2 2 L
VG

Linear region

ID =

Saturation region
ID VS VB VD VG VB VD VS ID ID VS VD VG

Prof. Gaetano Palumbo

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Channel Length Modulation


VG > Vto V =0 S Oxide Source n+ p y=0 y L' L L Drain n+ VD > VDSsat ID

L ' = L L

L L

1 VDS

0.01 V-1 < < 0.05 V-1 (20 V < 1/ < 100 V )

C W I D ( sat ) = n ox (VG Vto ) 2 (1 + VDS ) 2 L

is function of the length L. It is is higher for lower L More accurately L VDS VDSAT
Prof. Gaetano Palumbo 17

Short channel MOS


Due to the high Electric field n is not constant
n = no 1+ VDS + ( VGS Vt ) Ey L

Longitudinal field In saturation VDS= VDSsat = 0.01 0.8

Vertical field
= 1 + 1 = no Ey L E y L vmax L

no C W (VG Vto ) 2 (1 + VDS ) I D ( sat ) = ox 2 1 + (VGS Vt ) L


Prof. Gaetano Palumbo 18

Sub-threshold MOS
If VGS Vt the transistor is not completely off: Subthreshoil region (or weak inversion)
VGS V DS W nVT nV ID = Kx e 1 e T L

Exponential model like bipolar transistor Kx process parameter, n1.5

Prof. Gaetano Palumbo

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