ANALYSIS AND DESIGN OF DIGITAL CIRCUITS [18EC34]

UNIT-V

Design of a Processor Unit

INTRODUCTION
A processor unit is that part of a digital system or a digital computer that implements the
operations in the system. It is comprised of a number of registers and the digital functions that
implement arithmetic, logic, shift, and transfer microoperations. The processor unit, when
combined with a control unit that supervises the sequence of microoperations, is called a central
processor unit or CPU. This chapter is concerned with the organization and design of the
processor unit.

The number of registers in a processor unit may vary from just one processor register to as many
as 64 registers or more. Some older computers came with only one processor register. In some
cases a special-purpose digital system may employ a single processor register. However, since
registers and other digital functions are inexpensive when constructed with integrated circuits, all
recent computers employ a large number of processor registers and route the information among
them through common buses.

An operation may be implemented in a processor unit either with a single microoperation or with
a sequence of microoperations. For example, the multiplication of two binary numbers stored in
two registers may be implemented with a combinational circuit that performs the operation by
means of gates. As soon as the signals propagate through the gates, the product is available and
can be transferred to a destination register with a single clock pulse. Alternatively, the
multiplication operation may be performed with a sequence of add and shift microoperations.
The method chosen for the implementation dictates the amount and type of hardware in the
processor unit.
All computers, except the very large and fast ones, implement the involved operations by means
of a sequence of microoperations. In this way, the processor unit need only have circuits that
implement simple, basic microoperations such as add and shift. Other operations, such as
multiplication, division, and floating-point arithmetic, are generated in conjunction with the
control unit. The control unit is designed to sequence the microoperations to achieve other
operations which are not included in the basic set.
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The digital function that implements the microoperations on the information stored in processor
registers is commonly called an arithmetic logic unit or ALU. To perform a microoperation, the
control routes the source information from registers into the inputs of the ALU. The ALU
receives the information from the registers and performs a given operation as specified by the
control. The result of the operation is then transferred to a destination register. By definition, the
ALU is a combinational circuit; thus the entire register-transfer operation can be performed
during one clock pulse interval. All register-transfer operations, including interregister transfers,
in a typical processor unit are performed in one common ALU; otherwise, it would be necessary
to duplicate the digital functions for each register. The shift microoperations are often performed
in a separate unit. The shift unit is usually shown separately, but sometimes this unit is implied to
be part of the overall arithmetic and logic unit.
A computer CPU must manipulate not only data but also instruction codes and addresses coming
from memory. The register that holds and manipulates the operation code of instructions is
considered to be part of the control unit. The registers that hold addresses are sometimes
included as part of the processor unit, and the address information is manipulated by the common
ALU. In some computers, the registers that hold addresses are connected to a separate bus and
the address information is manipulated with separate digital functions.
This chapter presents a few alternatives for the organization and design of a processor unit. The
design of a particular arithmetic logic unit is undertaken to show the design process involved in
formulating and implementing a common digital function capable of performing a large number
of microoperations. Other digital functions considered and designed in this chapter are a shifter
unit and a general-purpose processor register, commonly called an accumulator.

PROCESSOR ORGANIZATION
The processor part of a computer CPU is sometimes referred to as the data path of the CPU
because the processor forms the paths for the data transfers between the registers in the unit. The
various paths are said to be controlled by means of gates that open the required path and close all
others. A processor unit can be designed to fulfill the requirements of a set of data paths for a

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specific application. The gating of the data paths is achieved through the decoders and
combinational circuit which comprise the control section of the unit.

In a well-organized processor unit, the data paths are formed by means of buses and other
common lines. The control gates that formulate the given path are essentially multiplexers and
decoders whose selection lines specify the required path. The processing of information is done
by one common digital function whose data path can be specified with a set of common selection
variables. A processor unit that has a well-structured organization can be used in a wide variety
of applications. If constructed within an integrated circuit, it becomes available to many users,
each of which may have a different application.

In this section, we investigate a few alternatives for organizing a general-purpose processor unit.
All organizations employ a common ALU and shifter. The differences in organizations are
mostly manifested in the organization of the registers and their common path to the ALU.

Bus Organization
When a large number of registers are included in a processor unit, it is most efficient to connect
them through common buses or arrange them as a small memory having very fast access time.
The registers communicate with each other not only for direct data transfers, but also while
performing various microoperations. A bus organization for four processor registers is shown in
Fig. 5-1. Each register is connected to two multiplexers (MUX) to form input buses A and B. The
selection lines of each multiplexer select one register for the particular bus. The A and B buses
are applied to a common arithmetic logic unit. The function selected in the ALU determines the
particular operation that is to be performed. The shift microoperations are implemented in the
shifter. The result of the microoperation goes through the output bus S into the inputs of all
registers. The destination register that receives the information from the output bus is selected by
a decoder. When enabled, this decoder activates one of the register load inputs to provide a
transfer path between the data on the S bus and the inputs of the selected destination register.

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The output bus S provides the terminals for transferring data to an external destination. One
input of multiplexer A or B can receive data from the outside environment when it is necessary to
transfer external data into the processor unit.

A processor unit may have more than four registers. The construction of a bus-organized
processor with more registers requires larger multiplexers and decoder; otherwise, it is similar to
the organization depicted in Fig. 5-1.

Figure5-1 Processor registers and ALU connected through common buses

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The control unit that supervises the processor bus system directs the information flow through
the ALU by selecting the various components in the unit. For example, to perform the
microoperation:
R1 ←R2 + R3
The control must provide binary selection variables to the following selector inputs:
1. MUX A selector: to place the contents of R2 onto bus A.
2. MUX B selector: to place the contents of R3 onto bus B.
3. ALU function selector: to provide the arithmetic operation A + B.
4. Shift selector: for direct transfer from the output of the ALU onto output
bus S (no shift).
5. Decoder destination selector: to transfer the contents of bus S into RI.
The five control selection variables must be generated simultaneously and must be available
during one common clock pulse interval. The binary information from the two source registers
propagates through the combinational gates in the multiplexers, the ALU, and the shifter, to the
output bus, and into the inputs of the destination register, all during one clock pulse interval.
Then, when the next clock pulse arrives, the binary information on the output bus is transferred
into R 1. To achieve a fast response time, the ALU is constructed with carry look-ahead circuits
and the shifter is implemented with combinational gates.

When enclosed in an IC package, a processor unit is sometimes called a register and arithmetic
logic unit or RALU. It is also called by some vendors a bit-slice microprocessor. The prefix
micro refers to the small physical size of the integrated circuit in which the processor is enclosed.
Bit-slice refers to the fact that the processor can be expanded to a processor unit with a larger
number of bits by using a number of ICs. For example, a 4-bit-slice microprocessor contains
registers and ALU for manipulating 4-bit data. Two such ICs can be combined to construct an 8-
bit processor unit. For a 16-bit processor, it is necessary to use four ICs and connect them in
cascade. The output carry from one ALU is connected to the input carry of the next higher-order
ALU, and the serial output and input lines of the shifters are also connected in cascade. A bit-
slice microprocessor should be distinguished from another type of IC called a microprocessor.
The former is a processor unit, whereas a microprocessor refers to an entire computer CPU
enclosed in one IC package.

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Scratchpad Memory:
The registers in a processor unit can be enclosed within a small memory unit. When included in a
processor unit, a small memory is sometimes called a scratchpad memory. The use of a small
memory is a cheaper alternative to connecting processor registers through a bus system. The
difference between the two systems is the manner in which information is selected for transfer
into the ALU. In a bus system, the information transfer is selected by the multiplexers that form
the buses. On the other hand, a single register in a group of registers organized as a small
memory must be selected by means of an address to the memory unit. A memory register can
function just as any other processor register as long as its only function is to hold binary
information to be processed in the ALU.

A scratchpad memory should be distinguished from the main memory of the computer. Contrary
to the main memory which stores instructions and data, a small memory in a processor unit is
merely an alternative to connecting a number of processor registers through a common transfer
path. The information stored in the scratchpad memory would normally come from the main
memory by means of instructions in the program.

Consider, for example, a processor unit that employs eight registers of 16 bits each. The registers
can be enclosed within a small memory of eight words of 16 bits each, or an 8 X 16 RAM. The
eight memory words can be designated RO through R7, corresponding to addresses 0 through 7,
and constitute the registers for the processor.

A processor unit that uses a scratch pad memory is shown in Fig. 5-2. A source register is
selected from memory and loaded into register A. A second source register is selected from
memory and loaded into register B. The selection is done by specifying the corresponding word
address and activating the memory read input. The information in A and B is manipulated in the
ALU and shifter. The result of the operation is transferred to a memory register by specifying its
word address and activating the memory-write input control. The multiplexer in the input of the
memory can select input data from an external source.

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Assume that the memory has eight words, so that an address must be specified with three bits. To
perform the operation:
R1 ←R2 + R3
The control must provide binary selection variables to perform the following sequence of three
microoperations:

T1: A ← M [010] Read R2 into register A

T2: B ← M [011] Read R3 into register B
T3: M [001] ← A + B Perform operation in ALU and transfer result to R1

Control function T1 must supply an address of 010 to the memory and activate the read and load
A inputs. Control function T2 must supply an address 011 to the memory and activate the read
and load B inputs. Control function T3 must supply the function code to the ALU and.

Figure 5-2 Processor unit employing a scratcbpad memory

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shifter to perform an add operation (with no shift), apply an address 001 to the memory, select
the output of the shifter for the MUX, and activate the memory write input. The symbol M[xxx]
designates a memory word (or register) specified by the address given in the binary number xxx.

The reason for a sequence of three microoperations, instead of just one as in a bus-organized
processor, is due to the limitation of the memory unit. Since the memory unit has only one set of
address terminals but two source registers are to be accessed, two accesses to memory are needed
to read the source information. The third microoperation is needed to address the destination
register. If the destination register is the same as the second source register, the control could
activate the read input to extract the second-source information, followed by a write signal to
activate the destination transfer, without having to change the address value.

Some processors employ a 2-port memory in order to overcome the delay caused when reading
two source registers. A 2-port memory has two separate address lines to select two words of
memory simultaneously. In this way, the two source registers can be read at the same time. If the
destination register is the same

Figure 5-3 Processor unit with a 2-port memory

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as one of the source registers, then the entire microoperation can be done within one clock pulse
period.

The organization of a processor unit with a 2-port scratchpad memory is shown in Fig. 5-3. The
memory has two sets of addresses, one for port A and the other for port B. Data from any word in
memory are read into the A register by specifying an A address. Likewise, data from any word in
memory are read into the B register by specifying a B address. The same address can be applied
to the A address and the B address, in which case the identical word will appear in both A and B
registers. When enabled by the memory enable (ME) input, new data can be written into the
word specified by the B address. Thus the A and B addresses specify two source registers
simultaneously, and the B address always specifies the destination register. Figure 5-3 does not
show a path for external input and output data, but they can be included as in previous
organizations.

The A and B registers are, in effect, latches that accept new information as long as the clock
pulse, CP, is in the l-state, When CP goes to 0, the latches are disabled, and they hold the
information that was stored when CP was a 1. This eliminates any possible race conditions that
could occur while new information is being written into memory. The clock input controls the
memory read and write operations through the write enable (WE) input. It also controls the
transfers into the A and B latches. The waveform of one clock pulse interval is shown in the
diagram.

When the clock input is I, the' A and B latches are open and accept the information coming from
memory. The WE input is also in the l-state, This disables the write operation and enables the
read operation in the memory. Thus, when CP = I, the words selected by the A and B addresses
are read from memory and placed in registers A and B, respectively. The operation in the ALU is
performed with the data stored in A and B. When the clock input goes to 0, the latches are closed
and they retain the last data entered. If the ME input is enabled while WE = 0, the result of the
microoperation is written into the memory word defined by the B address. Thus, a
microoperation:
R1←R1+R2

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can be done within one clock pulse period. Memory register R I must be specified with the B
address, and R 2 with the A address.

Accumulator Register
Some processor units separate one register from all others and call it an accumulator register,
abbreviated AC or A register. The name of this register is derived from the arithmetic addition
process encountered in digital computers. The process of adding many numbers is carried out by
initially storing these numbers in other processor registers or in the memory unit of the computer
and clearing the accumulator to 0. The numbers are then added to the accumulator one at a time,
in consecutive order. The first number is added to 0, and the sum transferred to the accumulator.
The second number is added to the contents of the accumulator, and the newly formed sum
replaces its previous value. This process is continued until all numbers are added and the total
sum is formed. Thus, the register "accumulates" the sum in a step-by-step manner by performing
sequential additions between a new number and the previously accumulated sum.

The accumulator register in a processor unit is a multipurpose register capable of performing not
only the add microoperation, but many other microoperations as well. In fact, the gates
associated with an accumulator register provide all the digital functions found in an ALU.

Figure 5-4 shows the block diagram of a processor unit that employs an accumulator register.
The A register is distinguished from all other processor registers. In some cases the entire
processor unit is just the accumulator register and its associated ALU. The register itself can
function as a shift register to provide the shift microoperations, Input B supplies one external
source information. This information may come from other processor registers or directly from
the main memory of the computer. The A register supplies the other source information to the
ALU at input A. The result of an operation is transferred back to the A register and replaces its
previous content. The output from the A register may go to an external destination or into the
input terminals of other processor registers or memory unit.

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To form the sum of two numbers stored in processor registers, it is necessary

Figure 5-4 Processor with an accumulator register

to add them in the A register using the following sequence of microoperations:
T1: A ←0 clear A
T2: A ←A + R1 transfer R 1 to A
T3: A ←A + R2 add R2 to A

Register A is first cleared. The first number in R 1 is transferred into the A register by adding it to
the present zero content of A. The second number in R2 is then added to the present value of A.
The sum formed in A may be used for other computations or may be transferred to a required
destination.

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ARITHMETIC LOGIC UNIT [ALU]

An arithmetic logic unit (ALU) is a multioperation, combinational-logic digital function. It can
perform a set of basic arithmetic operations and a set of logic operations. The ALU has a number
of selection lines to select a particular operation in the unit. The selection lines are decoded
within the ALU so that k selection variables can specify up to 2k distinct operations.

Figure 5-5 shows the block diagram of a 4-bit ALU. The four data inputs from A are combined
with the four inputs from B to generate an operation at the F

Figure 5-5 Block diagram of a 4-bit ALU

outputs. The mode-select input S2 distinguishes between arithmetic and logic operations. The
two function-select inputs S1 and S0 specify the particular arithmetic or logic operation to be
generated. With three selection variables, it is possible to specify four arithmetic operations (with
S2 in one state) and four logic operations (with S2 in the other state). The input and output
carries have meaning only during an arithmetic operation.

The input carry in the least significant position of an ALU is quite often used as fourth selection
variables that can double the number of arithmetic operations. In this way, it is possible to
generate four more operations, for a total of eight arithmetic operations.

The design of a typical ALU will be carried out in three stages. First, the design of the arithmetic
section will be undertaken. Second, the design of the logic section will be considered. Finally,

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the arithmetic section will be modified so that it can perform both arithmetic and logic
operations.

DESIGN OF ARITHMETIC CIRCUIT

The basic component of the arithmetic section of an ALU is a parallel adder. A parallel adder is
constructed with a number of full-adder circuits connected in cascade. By controlling the data
inputs to the parallel adder, it is possible to obtain different types of arithmetic operations. Figure
5-6 demonstrates the arithmetic operations obtained when one set of inputs to a parallel adder is
controlled externally. The number of bits in the parallel adder may be of any value. The input
carry Cin goes to the full-adder circuit in the least significant bit position. The output carry Cout
comes from the full-adder circuit in the most significant bit position.

The arithmetic addition is Kchieved when one set of inputs receives a binary number A, the other
set of inputs receives a binary number B, and the input carry is maintained at 0. This is shown in
Fig. 5-6(a). By making Cin = 1 as in Fig. 5·6(b), it is possible to add 1 to the sum in F. Now
consider the effect of complementing all the bits of input B. With Cin =0, the output produces F
= A + B' , which is the sum of A plus the 1's complement of B. Adding 1 to this sum by making
Cin = 1, we obtain F = A + B' + 1, which produces the sum of A plus the 2's complement of B.
This operation is similar to a subtraction operation if the output carry is discarded. If we force all
0's into the B terminals, we obtain F = A + 0= A, which transfers input A into output F. Adding 1
through Cin as in Fig. 5-6(f), we obtain F = A + 1, which is the increment operation.

The condition illustrated in Fig. 5-6(g) inserts all l's into the B terminals. This produces the
decrement operation F = A-1. To show that this condition is indeed a decrement operation,
consider a parallel adder with n full-adder circuits.When the output carry is I, it represents the
number 2n because 2n in binary consists of a 1 followed by n 0's. Subtracting 1 from 2n, we
obtain 2n - 1, which in binary is a number of n 1's. Adding 2n - 1 to A, we obtain F = A + 2n - 1 =
2n + A - 1. If the output carry 2n is removed, we obtain F = A-1.

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Figure 5-6 Operations obtained by controlling one set of inputs to a parallel adder

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To demonstrate with a numerical example, let n = 8 and A = 5. Then:

A= 0000 1001 = (5)10
2n = 1 0000 0000 = (256)10
2n - 1= 1111 1111 = (255)10
A + 2n - 1 = 1 0000 1000 = (256 + 8)10
Removing the output carry 2n = 256, we obtain 8 = 5 - 1. Thus, we have decremented A by 1 by
adding to it a binary number with all l's.

The circuit that controls input B to provide the functions illustrated in Fig. 5-6 is called a true /
complement, one/zero element. This circuit is illustrated in Fig. 5-7. The two selection lines S1
and S0 control the input of each B terminal. The diagram shows one typical input designated by
Bi and an output designated by Yi. In a typical application, there are n such circuits for i = 1,2, ...
,n. As shown in the table of Fig. 5-7, when both S1 and S0 are equal to 0, the output Yi = 0,
regardless of the value of Bi. When S1S0 = 01, the top AND gate generates the value of Bi while
the bottom gate output is 0; so Yi = Bi. With S1S0= 10, the bottom AND gate generates the
complement of Bi to give Yi = Bi’ When S1S0 = 11, both gates are active and Yi = Bi + Bi' = 1.

A 4-bit arithmetic circuit that performs eight arithmetic operations is shown in Fig. 5-8. The four
full-adder (FA) circuits constitute the parallel adder. The carry into the first stage is the input
carry. The carry out of the fourth stage is the output carry. All other carries are connected
internally from one stage to the next. The selection variables are s1, s0 and Cin. Variables s1 and
s0 control all of the B inputs to the full-adder circuits as in Fig. 5-7. The A inputs go directly to
the other inputs of the full adders.
The arithmetic operations implemented in the arithmetic circuit are listed in Table 5-1. The
values of the Y inputs to the full-adder circuits are a function of

Figure 5-7 True/complement, one/zero circuit

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Figure 5-8 Logic diagram of arithmetic circuit

TABLE 5-1 Function table for the arithmetic circuit of fig 5.8
Function Select Y Equals Output Equals Function Equals
(S1S0Cin)
000 0 F=A Transfer A
001 0 F=A+1 Increment A
010 B F=A+B Add B to A
011 B F= A+B+1 Add B to A plus1
100 B’ F=A+B’ Add 1’s complement of B to A
101 B’ F= A+B’+1 Add 2’s complement of B to A
110 All 1’s F=A-1 Decrement A
111 All 1’s F= A Transfer A

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selection variables S1 and S0. Adding the value of Y in each case to the value of A plus the Cin
value gives the arithmetic operation in each entry. The eight operations listed in the table follow
directly from the function diagrams illustrated in Fig. 5-6.

This example demonstrates the feasibility of constructing an arithmetic circuit by means of a

parallel adder. The combinational circuit that must be inserted in each stage between the external
inputs Ai and Bi and the inputs of the parallel adder Xi and Yi is a function of the arithmetic
operations that are to be implemented. The arithmetic circuit of Fig. 5-8 needs a combinational
circuit in each stage specified by the Boolean functions:
Xi=Ai
Yi = Bis0 + Bi’s1 i = 1, 2, ... , n
where n is the number of bits in the arithmetic circuit. In each stage i, we use the same common
selection variables s1 and S0. The combinational circuit will be different if the circuit generates
different arithmetic operations.

Effect of Output Carry

The output carry of an arithmetic circuit or ALU has special significance, especially after a
subtraction operation. To investigate the effect of the output carry, we expand the arithmetic
circuit of Fig. 5-8 to n bits so that Cout =1 when the output of the circuit is equal to or greater than
2n. Table 5-2 lists the conditions for having an output carry in the circuit. The function F = A will
always have the output carry equal to 0. The same applies to the increment operation F =A + 1,
except when it goes from an all-1's condition to an.all-0's condition, at which time selection
variables S1 and so. Adding the value of Y in each case to the value of A plus the Cin value gives
the arithmetic operation in each entry. The eight operations listed in the table follow directly
from the function diagrams illustrated in Fig. 5-6.

This example demonstrates the feasibility of constructing an arithmetic circuit by means of a

parallel adder. The combinational circuit that must be inserted in each stage between the external
inputs Ai and Bi, and the inputs of the parallel adder Xi and Yi is a function of the arithmetic
operations that are to be implemented.

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TABLE 5-2 Effect of output carry in the arithmetic circuit of Fig. 5-8
Function Select Arithmetic Cout=1 if Comments
(S1S0Cin) Function
000 F=A Cout is always 0
001 F=A+1 A=2n-1 Cout=1 and F=0 if A=2n-1
010 F=A+B (A+B) 2n Overflow Occurs if Cout=1
011 F= A+B+1 (A+B) 2n-1 Overflow Occurs if Cout=1
100 F=A-B-1 A>B If Cout=0, then A<B and
F=1’s complement of (B-A)
101 F= A-B A B If Cout=0, then A<B and
F=2’s complement of (B-A)
110 F=A-1 A 0 Cout=1, except A=0
111 F= A Cout is always 1
The arithmetic circuit of Fig. 5-8 needs a combinational circuit in each stage specified by the
Boolean functions:
Xi=Ai
Yi = Bis0 + Bi’s1 i = 1, 2, ... , n
where n is the number of bits in the arithmetic circuit. In each stage i, we use the same common
selection variables s1 and s0. The combinational circuit will be different if the circuit generates
different arithmetic operations.

The operation F = A + b’ adds the l's complement of B to A. Remember from Section 1-5 that the
complement of B can be expressed arithmetically as 2n - 1 - B. The arithmetic result in the output
will be:
F = A + 2n – 1– B = 2n +A – B –1

If A > B, then (A - B) > 0 and F > (2n - 1), so that COUI = 1. Removing the output carry 2n from
this result gives:
F=A–B–l
which is a subtraction with borrow. Note that if A ≤ B, then (A - B) ≤ 0 and F ≤ (2n- 1), so that
Cout=0. For this condition it is more convenient to express the arithmetic result as:
F= (2n - 1) - (B - A)
which is the l's complement of B - A.

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The condition for output carry when F = A + B’ + 1 can be derived in a similar manner. B’ + 1 is
the symbol for the 2's complement of B. arithmetically, this is an operation that produces a
number equal to 2n - B. The result of the operation can be expressed as:
F= A + 2n - B = 2n + A – B
If A≤B, then (A - B) ≥ 0 and F≥ 2n, so that Cout = 1. Removing the output carry 2n, we obtain:

F=A – B

which is a subtraction operation. If, however, A < B, then (A - B) < 0 and F_ < 2n, so that Cout =
0. The arithmetic result for this condition can be expressed as:
F= 2n - (B - A)
which is the 2's complement of B - A. Thus, the output of the arithmetic subtraction is correct as
long as A ≥ B. The output should be B - A if B >A, but the circuit generates the 2's complement of
this number.
The decrement operation is obtained from F = A + (2n - 1) =2n + A-1. The output carry is always
1 except-when A = 0. Subtracting 1 from 0 gives -1, and -1 in 2's complement is 2n - 1, which is a
number with all l's. The last entry in Table 5-2 generates F = (2n - 1) + A + 1 = 2n + A. This
operation transfers A into F and gives an output carry of 1.

Design of Other Arithmetic Circuits

The design of any arithmetic circuit that generates a set of basic operations can be undertaken by
following the procedure outlined in the previous example. Assuming that all operations in the set
can be generated through a parallel adder, we start by obtaining a function diagram as in Fig. 5-6.
From the function diagram, we obtain a function table that relates the inputs of the full-adder
circuit to the external inputs. From the function table, we obtain the combinational gates that
must be added to each full-adder stage. This procedure is demonstrated in the following example.

(a) Function specification

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(b) Specifying combinational circuit

(c) Truth table and simplified equations

Figure 5-9 Derivation of an adder/subtractor circuit

EXAMPLE 5-1: Design an adder /subtractor circuit with one selection variable s and two inputs
A and B. When S = 0 the circuit performs A + B. When s = 1 the circuit performs A - B by taking
the 2's complement of B.

The derivation of the arithmetic circuit is illustrated in Fig. 5·9. The function diagram is shown
in Fig. 5-9(a). For the addition part, we need Cin = 0. For the subtraction part, we need the
complement of Band Cin = 1. The function table is listed in Fig. 5.9(b). When s = 0, Xi and r; of
each full adder must be equal to the external inputs Ai and Bi, respectively. When s = 1, we must
have Xi = Ai and Yi = Bi’ The input carry must be equal to the value of s. The diagram in (b)
shows the position of the combinational circuit in one typical stage of the arithmetic circuit. The
truth table in (c) is obtained by listing the eight values of the binary input variables. Output Xi is
made to be equal to input Ai in all eight entries. Output Yi is equal to Bi for the four entries when
s = 0. It is equal to the complement of Bi for the last four entries where s = 1. The simplified
output functions for the combinational circuit are:

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Figure 5-10 4-bit adder/subtractor circuit

Xi = Ai
Yi =Bi  S

The diagram of the 4-bit adder /subtractor circuit is shown in Fig. 5-10. Each input Bi requires
an exclusive-Ok gate. The selection variable s goes to one input of each gate and also to the input
carry of the parallel adder. The 4-bit adder/subtractor can be constructed with two ICs. One IC is
the 4-bit parallel adder and the other is a quadruple exclusive-OR gates.

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DESIGN OF LOGIC CIRCUIT

The logic microoperations manipulate the bits of the operands separately and treat each bit as a
binary variable. Table 2-6 listed 16 logic operations that can be performed with two binary
variables. The 16 logic operations can be generated in one circuit and selected by means of four
selection lines. Since all logic operations can be obtained by means of AND, OR, and NOT
(complement) operations, it may be more convenient to employ a logic circuit with just these
operations. For three operations, we need two selection variables. But two selection lines can
select among four logic operations, so we choose also the exclusive-OR (XOR) function for the
logic circuit to be designed in this and the next section.

The simplest and most straightforward way to design a logic circuit is shown in Fig. 5-11. The
diagram shows one typical stage designated by subscript i. The circuit must be repeated n times
for an n-bit logic circuit. The four gates generate the four logic operations OR, XOR, AND, and
NOT. The two selection variables in the multiplexer select one of the gates for the output. The
function table lists the output logic generated as a function of the two selection variables.

Figure 5-11 One stage of logic circuit

The logic circuit can be combined with the arithmetic circuit to produce one arithmetic logic
unit. Selection variables S1 and S0 can be made common to both sections provided we use a
third selection variable, S2, to differentiate between the two. This configuration is illustrated in
Fig. 5-12. The outputs of the logic and arithmetic circuits in each stage go through a multiplexer

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with selection variable S2, When S2 = 0, the arithmetic output is selected, but when S2 = 1, the
logic output is selected. Although the two circuits can be combined in this manner, this is not the
best way to design an ALU.

A more efficient ALU can be obtained if we investigate the possibility of generating logic
operations in an already available arithmetic circuit. This can be done by inhibiting all input
carries into the full-adder circuits of the parallel adder. Consider the Boolean function that
generates the output sum in a full-adder circuit:
Fi = Xi  Yi  Ci
The input carry Ci in each stage can be made to be equal to 0 when a selection variable S2 is
equal to 1. The result would be:
Fi = Xi  Yi
This expression is valid because of the property of the exclusive-OR operation x  0 = x. Thus,
with the input carry to each stage equal to 0, the full-adder circuits generate the exclusive-OR
operation.

Now consider the arithmetic circuit of Fig. 5-8. The value of Yj can be selected by means of the
two selection variables to be equal to either 0, Bi, Bi', or 1.

Figure 5-12 Combining logic and arithmetic circuits

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TABLE 5-3 Logic operations in one stage of arithmetic circuit

S2S1S0 Xi Yi Ci Fi=XiYi Operation Required Operation
100 Ai 0 0 Fi=Ai Transfer A OR
101 Ai Bi 0 Fi=AiBi XOR XOR
100 Ai Bi’ 0 Fi=Ai Ꙩ Bi Equivalence AND
111 Ai 1 0 Fi=Ai’ NOT NOT

The value of Xi is always equal to input Ai' Table 5-3 shows the four logic operations obtained
when a third selection variable S2 = 1. This selection variable forces Ci to be equal to 0 while S1
and S0 choose a particular value for Yi. The four logic operations obtained by this configuration
are transfer, exclusive-OR. equivalence, and complement. The third entry is the equivalence
operation because:
Ai  Bi’ = AiBi + Ai’Bi’ = AiʘBi
The last entry in the table is the NOT or complement operation because:
Ai  1 = Ai’
The table has one more column which lists the four logic operations we want to include in the
ALU. Two of these operations, XOR and NOT, are already available. The question that must be
answered is whether it is possible to modify the arithmetic circuit further so that it will generate
the logic functions OR and AND instead of the transfer and equivalence functions. This problem
is investigated in the next section .

DESIGNOF ARITHMETICLOGICUNIT
In this section, we design an ALU with eight arithmetic operations and four logic operations.
Three selection variables S2, S1 and S0 select eight different operations, and the input carry Cin is
used to select four additional arithmetic operations. With S2 = 0, selection variables S1 and S0
together with Cin will select the eight arithmetic operations listed in Table 5-1. With S2 = 1,
variables S1 and S0 will select the four logic operations OR, XOR, AND, and NOT.

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The design of an ALU is a combinational-logic problem. Because the unit has a regular pattern,
it can be broken into identical stages connected in cascade through the carries. We can design
one stage of the ALU and then duplicate it for the number of stages required. There are six inputs
to each stage: Ai, Bi, Ci, S2, S1 and S0. There are two outputs in each stage: output Fi and the carry
out Ci+1. One can formulate a truth table with 64 entries and simplify the two output functions.

Here we choose to employ an alternate procedure that uses the availability of a parallel adder.
The steps involved in the design of an ALU are as follows:
1. Design the arithmetic section independent of the logic section.
2. Determine the logic operations obtained from the arithmetic circuit in step 1, assuming
that the input carries to all stages are 0.
3. Modify the arithmetic circuit to obtain the required logic operations.
The third step in the design is not a straightforward procedure and requires a certain amount of
ingenuity on the part of the designer. There is no guarantee that a solution can be found or that
the solution uses the minimum number of gates. The example presented here demonstrates the
type of logical thinking sometimes required in the design of digital systems.

It must be realized that various ALUs are available in IC packages. In a practical situation, all
that one must do is search for a suitable ALU or processor unit among the ICs that are available
commercially. Yet, the internal logic of the IC selected must have been designed by a person
familiar with logic design techniques.

The solution to the first design step is shown in Fig. 5-8. The solution to the second design step
is presented in Table 5-3. The solution of the third step is carried out below.

From Table 5-3, we see that when S2 =1, the input carry C, in each stage must be O. With SlS0 =
00, each stage as it stands generates the function Fi= Ai. To change the output to an OR operation,
we must change the input to each full-adder circuit from Ai to Ai + Bi. This can be accomplished
by ORing Bi and Ai when S2S1S0 = 100.

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The other selection variables that give an undesirable output occur when S2S1S0 = 110. The unit
as it stands generates an output F; = AiʘBi, but we want to generate the AND operation Fi =
AiBi. Let us investigate the possibility of ORing each input Ai with some Boolean function Ki.
The function so obtained is then used for Xi when S2S1S0= 110:
Fi = Xi  Yi = (Ai+Ki)  Bi’ = AiBi+ KiBi + Ai’Ki’Bi’
Careful inspection of the result reveals that if the variable Ki = Bi, we obtain an output:

Fi = AiBi + Bi’Bi + AiBiBi’ = AiBi

Two terms are equal to 0 because BiBi' = 0. The result obtained is the AND operation as required.
The conclusion is that, if Ai is ORed with Bi’ when S2S1S0 = 110, the output will generate the
AND operation.

Figure 5-13 Logic diagram of arithmetic logic unit (ALU)

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The final ALU is shown in Fig. 5-13. Only the first two stages are drawn, but the diagram can be
easily extended to more stages. The inputs to each full-adder circuit are specified by the Boolean
functions:
Xi = Ai+S2S1’S0’Bi+S2S1S0’Bi’
Yi = S0Bi+S1Bi’
Zi = S2’Ci

When S2 = 0, the three functions reduce to:

Xi = Ai
Yi = S0Bi+S1Bi’
Zi = Ci

which are the functions for the arithmetic circuit of Fig. 5-8. The logic operations are generated
when S2 = 1. For S2S1S0 = 101 or 111, the functions reduce to:

Xi = Ai
Yi = S0Bi+S1Bi’
Ci = 0

Output Fi is then equal to Xj Yi and produces the exclusive-OR and complement operations as
specified in Table 5-3. When S2S1S0 = 100, each Ai is ORed with Bi to provide the OR operation
as discussed above. When S2S1S0 = 110, each Ai is ORed with Bi’ to provide the AND operation
as explained previously.
The 12 operations generated in the ALU are summarized in Table 5-4. The particular function is
selected through S2S1S0 > and Cin. The arithmetic operations are identical to the ones listed for
the arithmetic circuit. The value of Cin for the four logic functions has no effect on the operation
of the unit and those entries are marked with don't-care X's.

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Table 5-4 Function table for the ALU of Fig. 5-13

Selection Output Function
(S2S1S0Cin)
0000 F=A Transfer A
0001 F=A+1 Increment A
0010 F=A+B Addition
0011 F= A+B+1 Add with carry
0100 F=A-B-1 Subtract with borrow
0101 F= A-B Subtraction
0110 F=A-1 Decrement A
0111 F= A Transfer A
100X F=AꓦB OR
101X F=AB XOR
110X F=AɅB AND
111X F=A’ Complement A

STATUS REGISTER
The relative magnitudes of two numbers may be determined by subtracting one number from the
other and then checking certain bit conditions in the resultant difference. If the two numbers are
unsigned, the bit conditions of interest are the output carry and a possible zero result. If the two
numbers include a sign bit in the highest-order position, the bit conditions of interest are the sign
of the result, a zero indication, and an overflow condition. It is sometimes convenient to
supplement the ALU with a status register where these status-bit conditions are stored for
further analysis. Status-bit conditions are sometimes called condition-code bits or flag bits.

Figure 5-14 shows the block diagram of an 8-bit ALU with a 4-bit status register. The four status
bits are symbolized by C, S, Z. and V. The bits are set or cleared as a result of an operation
performed in the ALU.
1. Bit C is set if the output carry of the ALU is I. It is cleared if the output carry is O.
2. Bit S is set if the highest-order bit of the result in the output of the ALU (the sign bit) is 1. It is
cleared if the highest-order bit is O.
3. Bit Z is set if the output of the ALU contains ali D's, and cleared otherwise. Z = 1 if the result
is zero, and Z = 0 if the result is nonzero.

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4. Bit V is set if the exclusive-OR of carries C8 and C5 is 1, and cleared otherwise. This is the
condition for overflow when the numbers are in sign-2's-complement representation (see
Section 8-6). For the 8-bit ALU, V is set if the result is greater than 127 or less than - 128.

The status bits can be checked after an ALU operation to determine certain relationships that
exist between the values of A and B. If bit V is set after the addition of two signed numbers, it
indicates an overflow condition. If Z is set after an exclusive-OR operation, it indicates that A =
B. This is so because x  x = 0, and the exclusive-OR of two equal operands gives an all-O's
result which sets the Z bit. A single bit in A can be checked to determine if it is 0 or I by masking
all bits except the bit in question and then checking the Z status bit. For example, let A =
101x1100, where x is the bit to be checked. The AND operation of A with B = 00010000
produces a result 000x0000. If x = 0, the Z status bit is set, but if x = 1, the Z bit is cleared since
the result is not zero.

The compare operation is a subtraction of B from A, except that the result of the operation is not
transferred into a destination register, but the status bits are affected. The status register then
provides the information about the relative magnitudes of A and B. The status bits to consider
depend on whether we take the two numbers to be unsigned or signed and in 2's-complement
representation.

Figure 5-14 Setting bits in a status register

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Consider the operation A - B done with two unsigned binary numbers. The relative magnitudes of
A and B can be determined from the values transferred to the C and Z status bits. If Z = I, then
we know that A = B, since A - B = 0. If Z = 0, then we know that A ≠ B. From Table 5-2, we have
that C = 1 if A ≥ B and C = 0 if A < B. These conditions are listed in Table 5-5. The table lists
two other conditions. For A to be greater than but not equal to B (A > B), we must have C = 1 and
Z = 0. Since C is set when the result is 0, we must check Z to ensure that the result is not 0. For A
to be less than or equal to B (A≤B), the C bit must be 0 (for A < B) or the Z bit must be 1 (for A =
B). Table 5-5 also lists the Boolean functions that must be satisfied for each of the six
relationships.
TABLE: 5-5 Status bits after the subtraction of unsigned numbers (A - B)
Relation Condition of Status Bits Boolean Function
A>B C=1 and Z=0 CZ’
A≥B C=1 C
A<B C’ C’
A≤B C=0 or Z=1 C’+Z
A=B Z=1 Z
A≠B Z=0 Z’
Some computers consider the C bit to be a borrow bit after a subtraction operation A-B. An end
borrow does not occur if A ≥ B, but an extra bit must be borrowed when A < B. The condition for
a borrow is the complement of the output carry obtained when the subtraction is done by taking
the 2's complement of B. For this reason, a processor that considers the C bit to be a borrow after
a subtraction will complement the C bit after a subtraction or compare operation and denote this
bit as a borrow.

Now consider the operation A - B done with two signed binary numbers when negative numbers
are in 2's-complement form. The relative magnitudes of A and B can be determined from the
values transferred to the Z, S, and V status bits. If Z = 1, then we know that A = B; when Z =0,
we have that A ≠ B. If S =0, the sign of the result is positive, so A must be greater than B. This is
true if there was no overflow and V = 0. If the result overflows, we obtain an erroneous result. It
was shown in Section 8-5 that an overflow condition changes the sign of the result. Therefore, if

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S = I and V = I, it indicates that the result should have been positive and therefore A must be
greater than B.

Table 5-6 lists the six possible relationships that can exist between A and B and the
corresponding values of Z, S, and V in each case. For A - B to be greater than but not equal to
zero (A >B), the result must be positive and nonzero. Since a zero result gives a positive sign, we
must ensure that the Z bit is 0 to exclude the possibility of A =B. For A ≥ B, it is sufficient to
check for a positive sign when no overflow occurs or a negative sign when an overflow occurs.
For A <B, the result must be negative. If the result is negative or zero, we have that A ≤ B. The
Boolean functions listed in the table express the status-bit conditions in algebraic form.

TABLE 5·6 Status bits alter the subtraction of sign-2's complement numbers (A - B)

Relation Condition of Status Bits Boolean Function

A>B Z=0 and (S=0,V=0 or S=1,V=1) Z’(SꙨV)
A≥B S=0,V=0 or S=1,V=1 SꙨV
A<B S=1,V=0 or S=0,V=1 SV
A≤B S=1,V=0 or S=0,V=1or Z=1 SV +Z
A=B Z=1 Z
A≠B Z=0 Z’

DESIGN OF SHIFTER
The shift unit attached to a processor transfers the output of the ALU onto the output bus. The
shifter may transfer the information directly without a shift, or it may shift the information to the
right or left. Provision is sometimes made for no transfer from the ALU to the output bus. The
shifter provides the shift microoperations commonly not available in an ALU.

An obvious circuit for a shifter is a bidirectional shift-register with parallel load. The information
from the ALU can be transferred to the register in parallel and then shifted to the right or left. In
this configuration, a clock pulse is needed for the transfer to the shift register, and another pulse
is needed for the shift. These two pulses are in addition to the pulse required to transfer the
information from the shift register to a destination register.

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The transfer from a source register to a destination register can be done with one clock pulse if
the shifter is implemented with a combinational circuit. In a combinational-logic shifter, the
signals from the ALU to the output bus propagate through gates without the need for a clock
pulse. Hence, the only clock pulse needed in the processor system is for loading the data from
the output bus into the destination register.

A combinational-logic shifter can be constructed with multiplexers as shown in Fig. 5-15. The
two selection variables, H1 and H0, applied to all four multiplexers select the type of operation
in the shifter. With H1H0 = 00, no shift is executed and the signals from F go directly to the S
lines. The next two selection variables cause a shift-right operation and a shift-left operation.
When H1H0 = 11, the multiplexers select the inputs attached to 0 and as a consequence the S
outputs are also equal to 0, blocking the transfer of information from the ALU to the output bus.
Table 5·7 summarizes the operation of the shifter.

The diagram of Fig. 5-15 shows only four stages of the shifter. The shifter, of course, must
consist of n stages in a system with n parallel lines. Inputs IR and IL

Figure 5·15 4-bit combinational-logic shifter

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TABLE 5-7 Function table for shifter

H1 H0 Operation Function
0 0 SF Transfer F to S(no shift)
0 1 Sshr F Shift right F into S
1 0 Sshl F Shift left F into S
1 1 S0 Transfer 0’s to S

serve as serial inputs for the last and first stages during a shift-right or shift-left, respectively.
Another selection variable may be employed to specify what goes into IR or IL during the shift.
For example, a third selection variable, H2, when in one state can select a 0 for the serial input
during the shift. When H2 is in the other state, the information can be circulated around together
with the value of the carry status bit. In this way, a carry produced during an addition operation
can be shifted to the right and into the most significant bit position of a register.

PROCESSOR UNIT
The selection variables in a processor unit control the rnicrooperations executed within the
processor during any given clock pulse. The selection variables control the buses, the ALU, the
shifter, and the destination register. We will now demonstrate by means of an example how the
control variables select the microoperations in a processor unit. The example defines a processor
unit together with all selection variables. Then we will discuss the choice of control variables foi
some typical microoperations.

block diagram of a processor unit is shown in Fig. 5-16(a). It consists of seven registers R 1
through R7 and a status register. The outputs of the seven registers go through two multiplexers
to select the inputs to the ALU. Input data from an external source are also selected by the same
multiplexers. The output of the ALU goes through a shifter and then to a set of external output
terminals. The output from the shifter can be transferred to anyone of the registers or to an
external destination.

There are 16 selection variables in the unit, and their function is specified by a control word in
Fig. 5-16(b). The 16-bit control word, when applied to the selection variables in the processor,

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specifies a given microoperation. The control word is partitioned into six fields, with each field
designated by a letter name. All fields, except Cin, have a code of three bits. The three bits of A
select a source register for the input to left side of the ALU. The B field is the same, but it selects
the source information for the right input of the ALU. The D field selects a destination register.
The F field, together with the bit in Cin, selects a function for the ALU. The H field selects the
type of shift in the shifter unit.

The functions of all selection variables are specified in Table 5-8. The 3-bit binary code listed in
the table specifies the code for each of the five fields A, B, D, F, and H.

(a) Block diagram

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(b) Control word

Figure 5-16 Processor unit with control variables
The register selected by A, B, and D is the one whose decimal number is equivalent to the binary
number in the code. When the A or B field is 000, the corresponding multiplexer selects the input
data. When D = 000, no destination register is selected. The three bits in the F field, together
with the input carry Cin, provide the 12 operations of the ALU as specified in Table 5-4. Note
that there are two possibilities for F = A. In one case the carry bit C is cleared, and in the other
case it is set to 1 (see Table 5-2).

TABLE 5-8 Functions of control variables for the processor of Fig. 5-16

Binary Code Function of Selection Variables

A B D F with F with H
Cin=0 Cin=1
000 Input data Input data None A,C0 A+1 No shift
001 R1 R1 R1 A+B A+B+1 Shift-right ,IR=0
010 R2 R2 R2 A-B-1 A-B Shift-LEFT ,IL=0
011 R3 R3 R3 A-1 A,C1 0’s to output bus
100 R4 R4 R4 AꓦB - -
101 R5 R5 R5 AB - Circulate-right with C
110 R6 R6 R6 AɅB - Circulate-left with C
111 R7 R7 R7 A’ - -

The first four entries for the code in the H field specify the shift operations of Table 5-7. A third
selection variable is used to specify either a 0 for the serial inputs IR and IL or a circular shift with
the carry bit C. For convenience, we , designate a circular right-shift with carry by c/c and a
circular left-shift with carry. by clc, Thus, the statement:
R ← crc R
is an abbreviation for the statement:
R ← shr R, Rn ← C, C ← R1

is shifted to the right, its least significant bit R, goes to C, and the value of C goes into the most
significant bit position Rn.

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control word of 16 bits is needed to specify a microoperation for the processor unit. The most
efficient way to generate control words with so many bits is to store them in a memory unit
which functions as a control memory where all control words are stored, The sequence of control
words is then read from the control memory, one word at a time, to initiate the desired sequence
of microoperations. This type of control organization is called microprogramming.

The control word for a given microoperation can be derived directly from the selection variables
defined in Table 5-8. The subtract microoperation:
R1 ← R1 - R2
specifies R 1 for the left input of the ALU, R2 for the right input of the ALU, A - B for the ALU
operation, no shift for the shifter, and R 1 for the destination register. From Table 5-8, we derive
the control word for this operation to be

0010100010101000:

A B D F Cin H
001 010 001 010 1 000
The control words for this microoperation and a few others are listed in Table 5-5. The compare
operation is similar to the subtract microoperation, except that the difference is not transferred to
a destination register; only the status bits are affected. The destination field D for this case must
be 000. The transfer of R 4 into R5 requires an ALU operation F = A. The source A is 100 and
the destination D is 101. The B selection code could be anything because the ALU does not use
it. This field is marked with 000 in the table for convenience, but any other 3-bit code could be
used.
To transfer the input data into R 6, we must have A = 000 to select the external input and D = 110
to select the destination register. Again the value of B does not matter and the ALU function is F
= A. To output data from R7, we make A = 111 and D = 000 (or 111). The ALU operation F = A
places the information from R7 into the output bus.

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It is sometimes necessary to clear or set the carry bit before a circular-shift operation. This can be
done with an ALU select code 0000 or 0111. With the first select code the C bit is cleared, and
with the second code the C bit is set. The transfer R 1←R 1, C ← 0 does not change the contents
of the register, but it clears C and V. The Z and S status bits are affected in the usual manner. If R
1 = 0, then Z is set to 1; otherwise, it is cleared. The S bit is set to the value of the sign bit in R1.

The clock pulse that triggers the destination register also transfers the status bits from the ALU
into the status register. The status bits are affected after the arithmetic operations. The C and V
status bits are left unchanged during a logic operation, since these bits have no meaning for the
logic operations. In some processors, it is customary not to change the value of carry bit C after
an increment or decrement operation as well.

TABLE 5-9 Examples of microoperations for processor

Control Word
Microoperation A B D F CIN H Function
R1R1-R2 001 010 001 010 1 000 Subtract R2 from R1
R3-R4 011 100 000 010 1 000 Compare R3 and R4
R5R4 100 000 101 000 0 000 Transfer R4 to R5
R6Input 000 000 110 000 0 000 Input data to R6
OutputR7 111 000 000 000 0 000 Output data from R7
R1R1,C0 001 000 001 000 0 000 Clear carry bit C
R3shl R3 011 011 011 100 0 010 Shift-left R3 with IL=0
R1crc R1 001 001 001 100 0 101 Circulate-right R1 with carry
R20 000 000 010 000 0 011 Clear R2
If we want to place the contents of a register into the shifter without changing the carry bit, we
can use the OR logic operation with the same register selected for both ALU inputs A and B. The
operation:
R←RVR
does not change the value of register R.However, it does place the contents of R into the inputs of
the shifter, and it does not change the values of status bits C and V.

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The examples in Table 5-9 discussed thus far use the shift-select code 000 for the H field to
indicate a no-shift operation. To shift the contents of a register, the value of the register must be
placed into the shifter without any change through the ALU. The shift-left microoperation
statement:
R3 ← Shl R3
specifies the code for the shift select but not the code for the ALU. The contents of R 3 can be
placed into the shifter by specifying an OR operation between R 3 and itself. The shifted
information returns to R 3 if R 3 is specified as the destination register. This requires that select
fields A, B, and D have the code 011 for R3, that the ALU function code be 1000 for the OR
operation, and that the shift-select H be 010 for the shift-left.

The circular shift-right with carry of register R I is symbolized by the statement:

R1 ← crc R1

This statement specifies the code for the shifter, but not the code for the ALU. To place the
contents of R 3 into the output terminals of the ALU without affecting the C bit, we use the OR
operation as before. In this way, the C bit is not affected by the ALU operation but may be
changed because of the circular shift.

The last example in Table 5-9 shows the control word for clearing a register to 0. To clear
register R2, the output bus is made to contain al 0's, with H = 011. The destination field D is
made equal to the code for register R2.

It is obvious from these examples that many more microoperations can be generated in the
processor unit. A processor unit with a complete set of microoperations is a general-purpose
device that can be adapted for many applications. The register-transfer method is a convenient
tool for specifying the operations in symbolic form in a digital system that employs a general-
purpose processor unit. The system is first defined with a sequence of microoperation statements
in the register-transfer method of notation or in any other suitable equivalent notation. A

Unit 5-Design of a Processor Unit Page 38

 ANALYSIS AND DESIGN OF DIGITAL CIRCUITS [18EC34]

control function here is represented not by a Boolean function, but rather by a string of binary
variables called a control word. The control word for each microoperation is derived from the
function table of the processor.

The sequence of control words for the system is stored in a control memory. The output of the
control memory is applied to the selection variables of the processor. By reading consecutive
control words from memory, it is possible to sequence the microoperations in the processor.
Thus, the entire design can be done by means of the register-transfer method which, in this
particular case, is referred to as the microprogramming method.

Unit 5-Design of a Processor Unit Page 39