UNIT II

VLSI Circuit Design Processes:

• VLSI Design Flow,

• MOS Layers,
• Stick Diagrams,
• Design Rules and Layout,
• 2 μm CMOS Design rules for wires,
• Contacts and Transistors Layout Diagrams for NMOS and
CMOS Inverters and Gates,
• Scaling of MOS circuits.
VLSI DESIGN FLOW

A design flow is a sequence of operations that transform the IC designers’

intention (usually represented in RTL: register transfer level format) into layout GDSII
data (Graphic Design System or Geometrical data base standard for information
interchange ).

A well-tuned design flow can help designers go through the chip-creation process
relatively smoothly and with a decent chance of error-free implementation. And, a
skilful IC implementation engineer can use the design flow creatively to shorten the
design cycle, resulting in a higher likelihood that the product will catch the market
window.
Front-end design (Logical Design):
1. Design entry – Enter the design in to an ASIC design system using a hardware
description language (HDL) or schematic entry
2. Logic synthesis – Generation of net list (logic cells and their connections) from HDL
code. Logic synthesis consists of following steps: (i) Technology independent Logic
optimization (ii) Translation: Converting Behavioral description to structural domain (iii)
Technology mapping or Library binding
3. System partitioning - Divide a large system into ASIC-sized pieces

4. Pre-layout simulation - Check to see if the design functions correctly.

Gate level functionality and timing details can be verified.
Back-end design (Physical design):
5. Floor planning - Arrange the blocks of the netlist on the chip
6. Placement - Decide the locations of cells in a block
7. Routing - Make the connections between cells and blocks
8. Circuit Extraction - Determine the resistance and capacitance of the interconnect
9. Post-layout simulation - Check to see the design still works with the added loads of
the interconnect
Partitioning
MOS LAYERS

MOS design is aimed at turning a specification into masks for processing silicon to
meet the specification. We have seen that MOS circuits are formed on four basic layers
• N-diffusion
• P-diffusion
• Poly Si
• Metal
which are isolated from one another by silicon dioxide insulating layers. The thin oxide
(thinox) mask region includes n-diffusion, p-diffusion, and transistor channels.
Polysilicon and thinox regions interact so that a transistor is formed where they cross one
another.

STICK DIAGRAMS

A stick diagram is a diagrammatic representation of a chip layout that helps to abstract a

model for design of full layout from traditional transistor schematic. Stick diagrams are
used to convey the layer information with the help of a color code.
“A stick diagram is a cartoon of a layout.”
The designer draws a freehand sketch of a layout, using colored lines to represent the
various process layers such as diffusion, metal and polysilicon. Where polysilicon
crosses diffusion, transistors are created and where metal wires join diffusion or
polysilicon, contacts are formed. For example, in the case of nMOS design,
• Green color is used for n-diffusion
• Red for polysilicon
• Blue for metal
• Yellow for implant, and
• Black for contact areas.
Monochrome encoding is also used in stick diagrams to represent the layer information.
Stick Diagrams – NMOS Encoding
Stick Diagrams –Some Rules

Rule 1:

When two or more ‘sticks’ of the same type cross or touch each other that
represents electrical contact.

Rule 2:
When two or more “sticks” of different type cross or touch each other there is no
electrical contact. (If electrical contact is needed we have to show the connection
explicitly)

Rule 3:

When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

nMOS Design Style :

To understand the design rules for nMOS design style, let us consider a single metal,
single polysilicon nMOS technology.
The layout of nMOS is based on the following important
features.

✓ n-diffusion [n-diff.] and other thin oxide regions [thinox] (green) ;

✓ polysilicon 1 [poly.]-since there is only one polysilicon layer here (red);
✓ metal 1 [metal]-since we use only one metal layer here (blue);
✓ implant (yellow);
✓ contacts (black or brown [buried]).

A transistor is formed wherever poly. crosses n-diff. (red over green) and all diffusion
wires (interconnections) are n-type (green).When starting a layout,
• the first step normally taken is to draw the metal (blue) VDD and GND rails in
parallel allowing enough space between them for the other circuit elements which
will be required.
• Next, thinox (green) paths may be drawn between the rails for inverters and inverter
based logic as shown in Fig. below.
• Inverters and inverter- based logic comprise a pull-up structure, usually a depletion
mode transistor, connected from the output point to VDD and a pull down structure
of enhancement mode transistors suitably interconnected between the output point
and GND. This is illustrated in the Fig.(b).
• remembering that poly. (red) crosses thinox (green)wherever transistors are required.
• One should consider the implants (yellow) for depletion mode transistors and also
consider the length to width (L:W) ratio for each transistor.
• These ratios are important particularly in nMOS and nMOS- likecircuits.
NMOS AND GATE

Figure :Transistor Circuit of NMOS AND Figure : Stick Diagram of NMOS

Gate. AND Gate.

Figure : Layout of NMOS AND Gate.

NMOS OR GATE

Figure : Transistor Circuit of NMOS OR Gate. Figure: Stick Diagram of NMOS OR Gate.

Figure 31. Layout of NMOS OR Gate.

NMOS INVERTER (NOT) GATE

Figure : Transistor Circuit of NMOS NOT Figure : Stick Diagram of NMOS

Gate. NOT Gate.
Figure: Layout of NMOS NOT Gate.
Transistor Circuit of NMOS NAND Gate. Stick Diagram of NMOS NAND
Gate.
Layout of NMOS NAND Gate.
2-i/p NOR Gate

Transistor Circuit of NMOS NOR Gate. Stick Diagram of NMOS NOR Gate.
Layout of NMOS NOR Gate
CMOS ENCODING
Rule:
In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All PMOS must lie on
one side of the line(ABOVE) and all NMOS will have to be on the other side(BELOW).

CMOS Design Style:

The CMOS design rules are almost similar and extensions of n-MOS design rules except the
Implant (yellow) and the buried contact (brown). In CMOS design Yellow is used to identify p
transistors and wires, as depletion mode devices are not utilized. The two types of transistors 'n' and
'p', are separated by the demarcation line (representing the p-well boundary) above which all p-type
devices are placed (transistors and wires (yellow). The n-devices (green) are consequently placed
below the demarcation line and are thus located in the p-well as shown in the diagram below.

Diffusion paths must not cross the demarcation line and n-diffusion and p-diffusion wires
must not join. The 'n' and 'p' features are normally joined by metal where a connection is
needed. Their geometry will appear when the stick diagram is translated to a mask layout. However,
one must not forget to place crosses on VDD and Vss rails to represent the substrate and p-well
connection respectively.
The design style is explained by taking the example the design of a inverter. The design
begins with the drawing of the VDD and Vss rails in parallel and in metal and the creation of an
(imaginary) demarcation line in-between, as shown in Fig.below. The n-transistors are then placed
below this line and thus close to Vss, while p-transistors are placed above the line and below VDD In
both cases, the transistors are conveniently placed with their diffusion paths parallel to the rails
(horizontal in the diagram) as shown in Fig.(b). A similar approach can be taken with transistors in
symbolic form.
 Fig. CMOS stick layout design style (a,b,c,d)

The n- along with the p-transistors are interconnected to the rails using the metal and connect
as Shown in Fig.. It must be remembered that only metal and poly-silicon can cross the
demarcation line but with that restriction, wires can run-in diffusion also. Finally, the remaining
interconnections are made as appropriate and the control signals and data inputs are added as
shown in the Fig.
CMOS Inverter

Transistor Circuit of CMOS NOT Gate Stick Diagram of CMOS NOT Gate.

Layout of CMOS NOT Gate.

2-INPUT CMOS NAND GATE
Requirements 2-PMOS enhancement transistors (connected in parallel)
2-NMOS enhancement transistors (connected in series)

Transistor Circuit of CMOS NAND Gate. Stick Diagram of CMOS NAND Gate.

Layout of CMOS NAND Gate.

CMOS NOR Gate
Requirements 2-PMOS enhancement transistors (connected in series)
2-NMOS enhancement transistors (connected in parallel)

Transistor Circuit of CMOS NOR Gate Stick Diagram of CMOS NOR Gate.

Layout of CMOS NOR Gate.