JNTUH B.Tech R22 EDC Unit 4
JNTUH B.Tech R22 EDC Unit 4
me/jntuh
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DEPARTMENT OF ECE GNITC
UNIT-4
JUNCTION FIELD EFFECT TRANSISTOR (FET)
SYLLABUS
Construction, Principle of operation, Pinch-Off Voltage, Volt-Ampere characteristic,
Comparison of BJT and FET, FET as Voltage Variable Resistor, MOSFET, MOSFET as a
capacitor.
COURSE OUTCOME
By the end of this chapter, students will be able to analyze the concepts of FETs and MOSFETs.
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DEPARTMENT OF ECE GNITC
FIELD EFFECT TRANSISTOR (FET) (Example Q: What is FET? What are the
types of FET?)
• The Field Effect Transistor, FET, is a three-terminal active device that uses an electric
field to control the current flow.
• It has a high input impedance which is useful in many circuits.
• FETs are unipolar devices, which means they use only one type of charge carrier
(electrons or holes) to control the current flow, unlike BJT in which current is because
of two types of charge carriers.
TYPES OF FET
Names of the Terminals Emitter, Base, and Collector Drain, Source, and Gate
Common Base, Common Emitter
Common Source, Common Drain,
Configurations & Common Collector
Common Gate configurations.
configurations
Bias type of input Forward bias in base (B) and Reverse bias in the source (S) and gate
circuit at active mode emitter (E) junction (G) junction
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DEPARTMENT OF ECE GNITC
Symbols
Input resistance Lower due to forward bias Higher due to reverse bias
JFET (Junction Field Effect Transistor) (Example Q: Explain the construction and
working of an N-Channel JFET with the help of its characteristics.)
1. N-Channel JFET
2. P-Channel JFET
• The structure of n-channel JFET consists of n-type substrate the two sides of which are
diffused with p-type material.
• The n-region is called the Channel as it forms a path between the Source and the Drain.
• The two p-regions are electrically connected and the common terminal is called Gate.
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WORKING:
• Let the voltage applied to the Gate terminal be 0 V i.e., VGS= 0 V, and the voltage VDS is
positive with a polarity as shown in the Figure.
• Under these bias conditions there is a flow of current IDS from Drain to Source the
magnitude of which depends on the VDS voltage.
• As VDS is applied, the electrons move toward the Drain terminal, and the Drain
Current (IDS) starts flowing.
• The Drain Current IDS is limited only by the n-channel resistance present in between
the Drain and Source.
• As the Drain-Source voltage VDS increases from 0V to a few volts, the Drain current
IDS will also increase as per Ohm's law as the channel resistance is constant.
• This region of operation is called the Ohmic region or more popularly as Triode
region.
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• As we further increase the voltage VDS it approaches a voltage level called Vp (pinch
off), the depletion region widens, and channel width reduces.
• This results in the reduction of the conduction path i.e., the resistance of the channel
increases.
Depletion Region width increases and Channel width reduces when VDS is increased
• As we further increase the voltage VDS, the two depletion regions touch each other as
shown in Figure below and the n-channel JFET is said to be pinched - off and the value
of VDS equals VP.
• As the value of the voltage VDS is further increased beyond the pinch-off voltage VP,
the two depletion regions that touch each other move across the length of the channel.
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DEPARTMENT OF ECE GNITC
• The Drain current levels off and remains constant (almost) with further increase in
the voltage VDS.
• The value of this drain current IDS is called IDSS and it is the maximum current for a
given n-channel JFET. The device is said to be operating in the saturation region.
• The n-channel JFET under these conditions where VDS > VP acts like a current source
generating a constant current of IDSS.
• It may be noted here that the maximum Drain current IDSS for a JFET is defined for
VGS = 0 V and VDS > VP.
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• In the Ohmic region the n-channel FET acts as a Voltage Controlled Resistor i.e., the
resistance of the device in this region of operation is controlled by the voltage applied at
the Gate terminal VGS.
• Sometimes the Ohmic region may also be called a Voltage Controlled Resistance
Region.
• The slope of the curve which indicates the resistance of the device between Drain and
Source for VDS = VP is a function of VGS.
• When VGS is negative (gate connected to the negative terminal of the battery), the width
of the depletion region of the gate channel increases.
• This effectively reduces the area of the channel and increases the channel resistance by
reducing the charge flow through the channel.
• As channel area decreases the drain current ID decreases for a given VDS. JFET is
operating like a resistance whose value is controlled by the Gate-to-Source voltage VGS.
• As the value of VGS is made more and more negative, the depletion region width increases
and it occupies the entire channel.
• This will result in the channel being completely depleted of charge carriers (electrons) in
an n-channel JFET. This situation may be considered as the effective disappearance of
the channel.
• As VGS is made sufficiently negative and reaches the value -VP,(negative Pinch-off
voltage) then the drain current almost becomes 0 mA and the device is said to be turned
OFF.
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DEPARTMENT OF ECE GNITC
Transfer Characteristics:
• As we understood that the drain current IDS depends on the drain voltage VDS and the gate
voltage VGS, thus
IDS = f (VDS, VGS)
• Transfer characteristics show a relation between the gate voltage VGS and the drain current
IDS and are plotted by keeping VDS constant.
• The curve is plotted by varying the value of VGS and finding the value of the ID.
• As in the case of an N-channel JFET, a negative voltage on the gate terminal decreases the
channel and thus decreases the drain current IDS current
• As the voltage VGS is increased beyond pinch-off voltage (VP) the drain current increases
till it becomes equal to IDSS at VGS = 0 V. (VGS (OFF))
• Equation for drain current under this condition can be given as
𝟐
𝑽𝑮𝑺
𝑰𝑫𝑺 ≅ 𝑰𝑫𝑺𝑺 [𝟏 − ]
𝑽𝑮𝑺(𝑶𝑭𝑭)
Where IDSS is the maximum drain to source current that results when VGS = 0 V and VDS >
VP (pinch-off voltage).
VGS (OFF) is the negative pinch-off voltage (as shown in the above graph) and the value of
VGS (OFF) is equal to | VP| in the above equation. i.e., VGS(OFF) = |VP|
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DEPARTMENT OF ECE GNITC
𝑽𝑫𝑺 𝑰
Thus 𝝁= × 𝑽𝑫𝑺
𝑰𝑫𝑺 𝑮𝑺
𝑽𝑫𝑺 𝑰
As = 𝒓𝒅 and 𝑽𝑫𝑺 = 𝒈𝒎
𝑰𝑫𝑺 𝑮𝑺
∴ 𝝁 = 𝒈𝒎 × 𝒓𝒅
Advantages of JFET
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• JFET can be fabricated in a smaller size, and as a result, they occupy less space in
circuits due to their smaller size.
Disadvantages of JFET
MOSFET is also known as Insulated Gate Field Effect Transistor (IGFET). It is basically of
two types.
1. Enhancement MOSFET
2. Depletion MOSFET
ENHANCEMENT MOSFET:
• The channel between the source and drain terminals is not physically present in an
Enhancement MOSFET, thus in the absence of gate voltage VGS no drain current will flow
through the FET.
• When sufficient gate voltage VGS is applied, the channel will be enhanced (and thus the
name) between source and drain semiconductors, and current will flow in the FET.
Enhancement MOS is of two types
1. N-Channel
2. P-Channel
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CONSTRUCTION:
• The working of MOSFET is similar to that of JFET where a battery is connected between
the Source terminal and Drain terminal with the negative terminal connected to the Source
and the positive terminal connected to the Drain.
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• This VDS voltage source will generate the Drain to Source current (IDS) only when the
Source and Drain semiconductors(N-type) are connected by an N-type channel.
• N-channel can be enhanced between the Source and Drain semiconductors by a positive
voltage (VGS > 0V) applied on the Gate terminal.
• The positive potential applied on the Gate (metal) terminal when increased, will be able
to draw the electrons present in the substrate to its surface as the Sio2 layer acts as a
dielectric allowing charge inversion between the Gate (metal) and the Substrate
(semiconductor).
• These electrons will accumulate between the Source and Drain semiconductors forming
an N-type channel that connects the Source and Drain.
• The value of VGS (> 0V) voltage at which the N-channel is created between the two N-
type semiconductors is known as threshold Voltage VT.
• Thus, when VGS > VT and when VDS > 0V, drain current IDS will flow through the
transistor.
• When VDS is further increased, a reverse bias is formed at the PN junction near the Drain
terminal resulting in a thick depletion region near the PN junction.
• Due to the increased depletion region the drain current will face more resistance near the
drain terminal that will force it to become constant and not increase further.
• This situation is called the pinch-off situation and the drain current is called the saturation
current IDS(SAT)
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DEPARTMENT OF ECE GNITC
• The voltage at which we get the saturation current is called saturation voltage VDS(SAT).
We can thus conclude, that pinch-off is reached when VGS > 0 (constant) and VDS =
VDS(SAT), ID = ID(SAT).
• From the graph, it is clear that the current IDS will become constant at a specific value of
VDS. current IDS increases only when the value of VGS is increased.
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Depletion MOSFET is of two types
1. N-Channel
2. P-Channel
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• When Gate terminal is connected to ground (VGS = 0V) and VDS is maintained positive,
drain current IDS flows from Drain to Source.
• With increase in VDS, IDS increases to a certain level until it becomes constant/saturated
(IDSS) at a particular value of VDS.
• When negative potential is applied on the Gate terminal, holes of the P-type substrate will
be attracted towards the negative Gate terminal and recombine with electrons in the N
channel.
• The (N)channel is thus depleted of negative charge carriers and drain current IDS will
decrease till it falls to zero value at a value of VGS voltage called pinch-off voltage.
Case-3 (VGS > 0V):
• With VGS > 0, the minority carriers of the p-type substrate, i.e., electrons, will get attracted
towards the gate terminal, thereby increasing the concentration of electrons in the N-
channel.
• As a result, the drain current IDS will increase and exceed the saturation current (IDSS).
Thus, we can say that, when VGS > 0 and VDS > 0, ID > IDSS.
• The graph shows that the current IDS will flow for both positive and negative values of
VGS.
• It can be observed that the drain current is less than the saturation current for the negative
value of gate voltage (VGS < 0V), whereas for the positive value of gate voltage (VGS >
0V), the drain current exceeds the saturation current.
• VGS = VP is also represented in this graph for which drain current is zero irrespective of
drain to source voltage (VDS).
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• In a MOSFET the Gate and the Channel are separated by a thin layer of SiO2, they form
a capacitance that varies along with gate voltage.
• MOSFET acts as a MOS capacitor and it is controlled by the input Gate to Source
voltage.
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• So, it will act like a voltage-controlled variable capacitor.
• Hence MOSFET can be used as a voltage-controlled capacitor.
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The drain resistance of
Drain The drain resistance of MOSFET is low
JFET is high and ranges
resistance of the order of 1 Ω to 50 Ω.
from 105 Ω to 106 Ω.
The addition of metal oxide increases the
Manufacturing The manufacturing cost of a
manufacturing cost of MOSFET. Thus,
cost JFET is less than MOSFET.
MOSFET is expensive than JFET.
For JFET, gate current is
Gate current For JFET, gate current is more.
more.
Characteristics JFET has more flat MOSFET has relatively less-flat
curve characteristics curve. characteristics curve.
In JFET, the conductivity of
In MOSFET, the conductivity is
Conductivity the device is controlled by
controlled by the charge carriers induced
control the reverse biasing of the
in the channel.
gate.
Signal handling The signal capacity of the MOSFET has more signal handling
capacity JFET is less. capacity than JFET.
JFET is mainly used in low MOSFET is extensively used in high
Applications
noise applications. noise applications.
1. Switching operation:
• One of the most common applications of MOSFETs is as switches in power electronics
circuits.
• A MOSFET can switch on and off very fast, which allows it to handle high frequencies and
reduce power losses.
• A MOSFET can also handle high currents and voltages, which makes it suitable for high-
power applications.
2. Amplifying Application:
• Radio-frequency amplifiers: These are circuits that amplify signals in the radio-frequency
range, such as radio waves or microwaves. A MOSFET can operate at high frequencies due
to its fast-switching speed.
• Audio amplifiers: These are circuits that amplify signals in the audio-frequency range, such
as sound waves or music. A MOSFET can operate with low distortion and noise due to its
high input impedance and low output impedance.
• Sensor amplifiers: These are circuits that amplify signals from sensors, such as
temperature, pressure, light, or motion sensors. A MOSFET can operate with low power
consumption and high reliability due to its simple structure and robustness.
3. Other Applications:
• Choppers: These are circuits that chop or modulate a DC voltage into an AC voltage with
variable frequency and amplitude. A MOSFET can be used as a chopper to control the duty
cycle of a square wave applied to a transformer or an LC circuit, which changes its output
characteristics.
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• Linear voltage regulators: A depletion-mode MOSFET can be used as a linear voltage
regulator to act as a variable resistor in series with the load, which adjusts its resistance
according to the load current.
• Digital circuits: A MOSFET can be used as a digital circuit element to implement logic
functions by using its switching behaviour.
• Microprocessors: A microprocessor consists of millions of transistors arranged in complex
architectures that execute various tasks. A MOSFET is one of the main types of transistors
used in microprocessors due to its high density, low power consumption, and fast speed.
CMOS:
Structure of CMOS:
• The power dissipation and consumption are very less in CMOS and it is faster, so it is
widely used than the bipolar circuits.
• CMOS consists of P- channel MOSFET (PMOS) and N-channel MOSFET (NMOS)
developed in a single semiconductor substrate.
Structure of CMOS
Working of CMOS
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• Same input voltage is used to turn ON one MOSFET and turn OFF other MOSFET.
• So, there is no need of pull up resistor in CMOS.
• NMOS is arranged in the pull-down network between the output and the ground.
• PMOS is arranged in the pull-up network.
• This pull-up and pull-down networks are arranged in such a way that when one network
is ON, the other network will be OFF.
Advantages of CMOS:
• Power consumption is less
• Large fan-out capability
• High noise immunity and noise margin
• Power dissipation is low
• Faster than NMOS
Disadvantages of CMOS:
• Manufacturing cost is high
• Propagation delay is higher than TTL and ECL
Applications of CMOS:
• Analog to digital converter
• Image sensors
• Amplifiers
• Static RAM
• Registers
• Microchip
• Microprocessors and microcontrollers
• Transceivers
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IMPORTANT QUESTIONS:
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OBJECTIVE QUESTIONS
1. FET is also called as a ____ transistor [C]
A. Uni-junction B. Bipolar
C. Unipolar D. Tripolar
4. ___ is the region that connects Drain and Source semiconductors and through which
(drain) current flows through FET. [A]
A. Channel B. Gate
C. Drain D. Source
7. The maximum Drain current (IDS) with gate voltage (VGS) zero is known as [A]
A. IDSS B. IGS
C. IGSS D. 0
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6. Ratio of Drain current IDS to Gate voltage VGS is called as mutual conductance (gm).
7. Amplification factor (µ) is the ratio of drain Voltage (VDS) to Gate voltage (VGS).
8. The value of VDS for which the Drain current (IDS) becomes constant when VGS = 0V is
9. Drain resistance (rd) is the ratio of Drain Voltage (VDS) to the Drain current (IDS) in a
FET.