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SEMICONDUCTOR TECHNICAL DATA by MTP2955V/D

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P–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
TMOS V is a new technology designed to achieve an on–resis- 12 AMPERES
tance area product about one–half that of standard MOSFETs. This 60 VOLTS
new technology more than doubles the present cell density of our RDS(on) = 0.230 OHM
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and TM
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients. D

New Features of TMOS V

• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology G
• Faster Switching than E–FET Predecessors

Features Common to TMOS V and TMOS E–FETS S CASE 221A–09, Style 5

• Avalanche Energy Specified TO–220AB
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit
Drain–to–Source Voltage VDSS 60 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc
Gate–to–Source Voltage — Continuous VGS ± 15 Vdc
Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGSM ± 25 Vpk

Drain Current — Continuous ID 12 Adc

Drain Current — Continuous @ 100°C ID 8.0
Drain Current — Single Pulse (tp ≤ 10 µs) IDM 42 Apk
Total Power Dissipation PD 60 Watts
Derate above 25°C 0.40 W/°C

Operating and Storage Temperature Range TJ, Tstg – 55 to 175 °C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS 216 mJ
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case RθJC 2.5 °C/W
Thermal Resistance — Junction to Ambient RθJA 62.5

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

REV 3

 Motorola TMOS
Motorola, Inc. 1997 Power MOSFET Transistor Device Data 1
MTP2955V
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3) V(BR)DSS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 — — Vdc
Temperature Coefficient (Positive) — 58 — mV/°C
Zero Gate Voltage Drain Current IDSS µAdc
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) — — 100
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 2.0) (3) VGS(th)
(VDS = VGS, ID = 250 µAdc) 2.0 2.8 4.0 Vdc
Threshold Temperature Coefficient (Negative) — 5.0 — mV/°C
Static Drain–to–Source On–Resistance (Cpk ≥ 1.5) (3) RDS(on) Ohm
(VGS = 10 Vdc, ID = 6.0 Adc) — 0.185 0.230

Drain–to–Source On–Voltage VDS(on) Vdc

(VGS = 10 Vdc, ID = 12 Adc) — — 2.9
(VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150°C) — — 2.5
Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) gFS 3.0 5.0 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss — 550 700 pF
Output Capacitance (VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
Coss — 200 280
f = 1.0 MHz)
Reverse Transfer Capacitance Crss — 50 100
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time td(on) — 15 30 ns
Rise Time (VDD = 30 Vdc,
Vd ID = 12 Adc,
Ad tr — 50 100
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω)) td(off) — 24 50
Fall Time tf — 39 80
Gate Charge QT — 19 30 nC

((VDS = 48 Vdc,
Vd , ID = 12 Adc,
Ad , Q1 — 4.0 —
VGS = 10 Vdc) Q2 — 9.0 —
Q3 — 7.0 —

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1) VSD Vdc
(IS = 12 Adc, VGS = 0 Vdc)
— 1.8 3.0
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)
— 1.5 —
Reverse Recovery Time trr — 115 — ns

((IS = 12 Adc,
Ad , VGS = 0 Vdc,
Vd , ta — 90 —
dIS/dt = 100 A/µs) tb — 25 —
Reverse Recovery Stored Charge QRR — 0.53 — µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance LD nH
(Measured from the drain lead 0.25″ from package to center of die) — 4.5 —

Internal Source Inductance LS nH

(Measured from the source lead 0.25″ from package to source bond pad) — 7.5 —
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Max limit – Typ
Cpk =
3 x SIGMA

2 Motorola TMOS Power MOSFET Transistor Device Data

 MTP2955V
TYPICAL ELECTRICAL CHARACTERISTICS

25 24
TJ = 25°C VGS = 10 V VDS ≥ 10 V TJ = – 55°C
9V 8V
21 100°C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

20 25°C
18
7V 15
15
12
10 6V 9

6
5
5V
3

0 0
0 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

0.40 0.250
VGS = 10 V TJ = 25°C
0.35 0.225
VGS = 10 V
0.30 TJ = 100°C 0.200

0.25 0.175
25°C 15 V
0.20 0.150

0.15 – 55°C 0.125

0.10 0.100

0.05 0.075

0 0.050
0 3 6 9 12 15 18 21 24 0 3 6 9 12 15 18 21 24
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Temperature and Gate Voltage

2.0 1000
RDS(on) , DRAIN–TO–SOURCE RESISTANCE

VGS = 0 V
1.8 VGS = 10 V
ID = 6 A
1.6
1.4 TJ = 125°C
I DSS , LEAKAGE (nA)
(NORMALIZED)

1.2
1.0 100 100°C

0.8
0.6
0.4
0.2
0 10
– 50 – 25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage

Temperature Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data 3

MTP2955V
POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge controlled. a voltage corresponding to the off–state condition when cal-
The lengths of various switching intervals (∆t) are deter- culating td(on) and is read at a voltage corresponding to the
mined by how fast the FET input capacitance can be charged on–state when calculating td(off).
by current from the generator.
The published capacitance data is difficult to use for calculat- At high switching speeds, parasitic circuit elements com-
ing rise and fall because drain–gate capacitance varies plicate the analysis. The inductance of the MOSFET source
greatly with applied voltage. Accordingly, gate charge data is lead, inside the package and in the circuit wiring which is
used. In most cases, a satisfactory estimate of average input common to both the drain and gate current paths, produces a
current (IG(AV)) can be made from a rudimentary analysis of voltage at the source which reduces the gate drive current.
the drive circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func-
t = Q/IG(AV) tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
During the rise and fall time interval when switching a resis-
mathematics. And finally, MOSFETs have finite internal gate
tive load, VGS remains virtually constant at a level known as
resistance which effectively adds to the resistance of the
the plateau voltage, VSGP. Therefore, rise and fall times may
driving source, but the internal resistance is difficult to mea-
be approximated by the following:
sure and, consequently, is not specified.
tr = Q2 x RG/(VGG – VGSP) The resistive switching time variation versus gate resis-
tf = Q2 x RG/VGSP tance (Figure 9) shows how typical switching performance is
where affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
VGG = the gate drive voltage, which varies from zero to VGG value of unity regardless of the switching speed. The circuit
RG = the gate drive resistance used to obtain the data is constructed to minimize common
and Q2 and VGSP are read from the gate charge curve. inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
During the turn–on and turn–off delay times, gate current is
power electronic loads are inductive; the data in the figure is
not constant. The simplest calculation uses appropriate val-
taken with a resistive load, which approximates an optimally
ues from the capacitance curves in a standard equation for
snubbed inductive load. Power MOSFETs may be safely op-
voltage change in an RC network. The equations are:
erated into an inductive load; however, snubbing reduces
td(on) = RG Ciss In [VGG/(VGG – VGSP)] switching losses.
td(off) = RG Ciss In (VGG/VGSP)

1800
VDS = 0 V VGS = 0 V TJ = 25°C
1600
Ciss
1400
C, CAPACITANCE (pF)

Crss
1200
1000
800
Ciss
600
400 Coss
200 Crss
0
10 5 0 5 10 15 20 25
VGS VDS

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4 Motorola TMOS Power MOSFET Transistor Device Data

 MTP2955V
10 30 1000

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)

QT VDD = 30 V
9 27 ID = 12 A
8 24 VGS = 10 V
Q1 Q2
TJ = 25°C
7 VGS 21
100

t, TIME (ns)
6 18
tr
5 15 tf
td(off)
4 12 td(on)
10
3 ID = 12 A 9
2 TJ = 25°C 6
1 Q3 3
VDS
0 0 1
0 2 4 6 8 10 12 14 16 18 20 1 10 100
QT, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

12
11 VGS = 0 V
TJ = 25°C
10
I S , SOURCE CURRENT (AMPS)

9
8
7
6
5
4
3
2
1
0
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis-
the maximum simultaneous drain–to–source voltage and sipated in the transistor while in avalanche must be less than
drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing
ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in
tion temperature and a case temperature (TC) of 25°C. Peak terms of energy, avalanche energy capability is not a
repetitive pulsed power limits are determined by using the constant. The energy rating decreases non–linearly with an
thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction tem-
discussed in AN569, “Transient Thermal Resistance–General
perature.
Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM) to–source avalanche at currents up to rated pulsed current
nor rated voltage (VDSS) is exceeded and the transition time (IDM), the energy rating is specified at rated continuous cur-
(tr,tf) do not exceed 10 µs. In addition the total power aver- rent (ID), in accordance with industry custom. The energy rat-
aged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the
(TJ(MAX) – TC)/(RθJC). accompanying graph (Figure 13). Maximum energy at cur-
A Power MOSFET designated E–FET can be safely used rents below rated continuous ID can safely be assumed to
in switching circuits with unclamped inductive loads. For reli- equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data 5

MTP2955V
SAFE OPERATING AREA

100 225
VGS = 15 V ID = 12 A

EAS, SINGLE PULSE DRAIN–TO–SOURCE

SINGLE PULSE 200
I D , DRAIN CURRENT (AMPS)

TC = 25°C 175

AVALANCHE ENERGY (mJ)

10 150
125
100 µs
1 ms 100
10 ms
1.0 dc 75

RDS(on) LIMIT 50
THERMAL LIMIT 25
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150 175
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE

0.2

0.1
0.05
0.1 P(pk)
0.02 RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
0.01
PULSE TRAIN SHOWN
SINGLE PULSE t1 READ TIME AT t1
t2 TJ(pk) – TC = P(pk) RθJC(t)
DUTY CYCLE, D = t1/t2
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

6 Motorola TMOS Power MOSFET Transistor Device Data

 MTP2955V
PACKAGE DIMENSIONS

NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
–T– PLANE
Y14.5M, 1982.
C 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
Q A 0.570 0.620 14.48 15.75
STYLE 5: B 0.380 0.405 9.66 10.28
1 2 3 U PIN 1. GATE C 0.160 0.190 4.07 4.82
2. DRAIN
H 3. SOURCE
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
K 4. DRAIN G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
V Q 0.100 0.120 2.54 3.04
J R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04

CASE 221A–09
ISSUE Z

Motorola TMOS Power MOSFET Transistor Device Data 7

MTP2955V

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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8 ◊ MTP2955V/D
Motorola TMOS Power MOSFET Transistor Device Data