Microprocessor System Design

BÙI QUỐC BẢO

([email protected])

University of Technology 1
 Outline

• Address decoding

• Chip select

• Memory configurations

University of Technology 2
 MEMORY INTERFACE

D7 - D0 D7 - D0

A19 - A0 A19 - A0

Simplified
Drawing of
MEMORY
8088 Minimum
Mode
cs

MEMR RD

MEMW WR

When Memory is selected? University of Technology 3

 Minimum Mode

220 bytes or 1MB

D7 - D0 D7 - D0

A19 - A0 A19 - A0

Simplified
Drawing of
MEMORY
8088 Minimum
Mode

MEMR RD

MEMW WR
CS

University of Technology 4
What are the memory locations of a
1MB (220 bytes) Memory?

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

00000 0000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

Example: 34FD0

0011 0100 11111 1101 0000

University of Technology 5
 Interfacing a 1MB Memory to the 8088 Microprocessor

AX 3F1C FFFFF 36
BX 0023 FFFFE 25
CX 0000 FFFFD 19
DX FCA1 : :
A19 A19
: :
: :
CS XXXX 20023 13
A0 A0
SS XXXX 20022 7D
DS 2000 20021 12
ES XXXX 20020 29
: :
D7 D7
BP XXXX : :
: :
SP XXXX 10008 8A
D0 D0
10007 F4
SI XXXX 10006 07
DI XXXX 10005 88
10004 42
MEMR RD
IP XXXX 10003 39
10002 27
10001 98
10000 45
: :
MEMW WR
: :
00001 95
CS 00000 23

University of Technology 6
Instead of Interfacing 1MB, what will happen if
you interface a 512KB Memory?

University of Technology 7
What are the memory locations of a
512KB (219 bytes) Memory?

A18 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

University of Technology 8
 Interfacing a 512KB Memory to the 8088 Microprocessor

AX 3F1C
BX 0023
CX 0000 What do we do with A19?
A19
DX FCA1
A18 A18 7FFFF 36
: : 7FFFE 25
CS XXXX
A0 A0 7FFFD 19
SS XXXX
: :
DS 2000
D7 D7 : :
ES XXXX
: : 20023 13
D0 D0 20022 7D
BP XXXX
20021 12
SP XXXX
MEMR RD 20020 29
: :
SI XXXX MEMW WR
: :
DI XXXX
00001 95
CS 00000 23
IP XXXX

University of Technology 9
 What if you want to read physical address A0023?

AX 3F1C
BX 0023
CX 0000
A19
DX FCA1
A18 A18 7FFFF 36
: : 7FFFE 25
CS XXXX
A0 A0 7FFFD 19
SS XXXX
: :
DS A000
D7 D7 : :
ES XXXX
: : 20023 13
D0 D0 20022 7D
BP XXXX
20021 12
SP XXXX
MEMR RD 20020 29
: :
SI XXXX MEMW WR
: :
DI XXXX
00001 95
CS 00000 23
IP XXXX

University of Technology 10
 What if you want to read physical
address A0023?

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

A0023 1010 0000 0000 0010 0011

A19 is not connected to the memory so

even if the 8088 microprocessor
outputs a logic “1”, the memory
cannot “see” this.
University of Technology 11
 What if you want to read physical
address 20023?

A18 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000
20023 0010 0000 0000 0010 0011

For memory it is the same as previous

one.

University of Technology 12
 Interfacing two 512KB Memory to the 8088 Microprocessor

AX 3F1C A19 7FFFF 36

BX 0023 A18 A18 7FFFE 25
CX 0000 : : 7FFFD 19
DX FCA1 A0 A0 : :
20023 13
D7 D7
CS XXXX 20022 7D
: :
SS XXXX 20021 12
D0 D0
DS 2000 20020 29
ES XXXX MEMR RD : :
MEMW WR 00001 95
BP XXXX CS 00000 23
SP XXXX

SI XXXX 7FFFF 12
DI XXXX A18 7FFFE 98
: 7FFFD 2C
IP XXXX A0 : :
20023 33
D7
20022 45
:
20021 92
D0
20020 A3
RD : :
WR 00001 D4
CS 00000 97

University of Technology 13
 Interfacing two 512KB Memory to the 8088 Microprocessor

• Problem: đụng độ bus (bus conflict). Hai RAM

sẽ xuất dữ liệu cùng lúc khi VXL thực hiện
lệnh đọc bộ nhớ
• Solution: dùng A19 làm bộ phân xử bus (bus
arbiter), trong trường hợp này có thể gọi là
bộ giải mã địa chỉ (address decoder).
• Khi A19 = 0, bộ nhớ thấp hơn được cho phép,
bộ nhớ cao bị cấm. Tương tự khi A19 = 1.

University of Technology 14
Interfacing two 512KB Memory to the 8088 Microprocessor

AX 3F1C A19 7FFFF 36

BX 0023 A18 A18 7FFFE 25
CX 0000 : : 7FFFD 19
DX FCA1 A0 A0 : :
20023 13
D7 D7
CS XXXX 20022 7D
: :
SS XXXX 20021 12
D0 D0
DS 2000 20020 29
ES XXXX MEMR RD : :
MEMW WR 00001 95
BP XXXX CS 00000 23
SP XXXX

SI XXXX 7FFFF 12
DI XXXX A18 7FFFE 98
: 7FFFD 2C
IP XXXX A0 : :
20023 33
D7
20022 45
:
20021 92
D0
20020 A3
RD : :
WR 00001 D4
CS 00000 97

University of Technology 15
 What are the memory locations of two
consecutive 512KB (219 bytes) Memory?

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

80000 1000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

University of Technology 16
 Interfacing two 512KB Memory to the 8088 Microprocessor

AX 3F1C A19 7FFFF 36

BX 0023 A18 A18 7FFFE 25
CX 0000 : : 7FFFD 19
DX FCA1 A0 A0 : :
20023 13
D7 D7
CS XXXX 20022 7D
: :
SS XXXX 20021 12
D0 D0
DS 2000 20020 29
ES XXXX MEMR RD : :

When the P outputs

MEMW WR 00001 95
BP XXXX CS 00000 23
SP XXXX
an address between
SI XXXX 80000 to 7FFFF,
00000 FFFFF, 7FFFF 12
DI XXXX A18 7FFFE 98
this memory is : 7FFFD 2C
IP XXXX
selected A0
20023
: :
33
D7
20022 45
:
20021 92
D0
20020 A3
RD : :
WR 00001 D4
CS 00000 97

University of Technology 17
 Interfacing two 512KB Memory to the 8088 Microprocessor

AX 3F1C A19 7FFFF 36

BX 0023 A18 A18 7FFFE 25
CX 0000 : : 7FFFD 19
DX FCA1 A0 A0 : :
20023 13
D7 D7
CS XXXX 20022 7D
: :
SS XXXX 20021 12
D0 D0
DS 2000 20020 29
ES XXXX MEMR RD : :
MEMW WR 00001 95
BP XXXX CS 00000 23
SP XXXX

SI XXXX 7FFFF 12
DI XXXX A18 7FFFE 98
: 7FFFD 2C
IP XXXX A0 : :
20023 33
D7
20022 45
:
20021 92
D0
20020 A3
RD : :
WR 00001 D4
CS 00000 97
University of Technology 18
 Interfacing two 512KB Memory to the 8088 Microprocessor

AX 3F1C A19 A19 7FFFF 36

BX 0023 A18 A18 A18 7FFFE 25
CX 0000 : : : 7FFFD 19
DX FCA1 A0 A0 A0 : :
20023 13
D7 D7 D7
CS XXXX 20022 7D
: : :
SS XXXX 20021 12
D0 D0 D0
DS 2000 20020 29
ES XXXX MEMR RD RD : :
MEMW WR WR 00001 95
BP XXXX CS 00000 23
SP XXXX

SI XXXX 7FFFF 12
DI XXXX A18 7FFFE 98
: 7FFFD 2C
IP XXXX A0 : :
20023 33
D7
20022 45
:
20021 92
D0
20020 A3
RD : :
WR 00001 D4
CS 00000 97
University of Technology 19
 What if we remove the lower memory?

AX 3F1C A19 7FFFF 36

BX 0023 A18 A18 7FFFE 25
CX 0000 : : 7FFFD 19
DX FCA1 A0 A0 : :
20023 13
D7 D7
CS XXXX 20022 7D
: :
SS XXXX 20021 12
D0 D0
DS 2000 20020 29
ES XXXX MEMR RD : :
MEMW WR 00001 95
BP XXXX CS 00000 23
SP XXXX

SI XXXX 7FFFF 12
DI XXXX A18 7FFFE 98
: 7FFFD 2C
IP XXXX A0 : :
20023 33
D7
20022 45
:
20021 92
D0
20020 A3
RD : :
WR 00001 D4
CS 00000 97

University of Technology 20
 What if we remove the lower memory?

AX 3F1C A19 7FFFF 36

BX 0023 A18 A18 7FFFE 25
CX 0000 : : 7FFFD 19
DX FCA1 A0 A0 : :
20023 13
D7 D7
CS XXXX 20022 7D
: :
SS XXXX 20021 12
D0 D0
DS 2000 20020 29
ES XXXX MEMR RD : :

When the P outputs

MEMW WR 00001 95
BP XXXX CS 00000 23
SP XXXX
an address between
SI XXXX 80000 to 7FFFF,
00000 FFFFF, no
DI XXXX
this memory
memory chipisis

!
IP XXXX
selected

University of Technology 21
 Full and Partial Decoding

• Full Decoding
– When all of the “useful” address lines are connected the
memory/device to perform selection
• Partial Decoding
– When some of the “useful” address lines are connected
the memory/device to perform selection
– Using this type of decoding results into roll-over
addresses

University of Technology 22
 Full Decoding

AX 3F1C A19 7FFFF 36

BX 0023 A18 A18 7FFFE 25
CX 0000 : : 7FFFD 19
DX FCA1 A0 A0 : :
20023 13
D7 D7
CS XXXX 20022 7D
: :
SS XXXX 20021 12
D0 D0
DS 2000 20020 29
ES XXXX MEMR RD : :
MEMW WR 00001 95
BP XXXX CS 00000 23
SP XXXX

SI XXXX
DI XXXX

IP XXXX

University of Technology 23
 Full Decoding

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

80000 1000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

A19 should be a logic “1” for the

memory chip to be enabled

University of Technology 24
 Full Decoding

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

Therefore if the microprocessor

outputs an address between 00000 to
7FFFF, whose A19 is a logic “0”, the
memory chip will not be selected
University of Technology 25
 Partial Decoding

AX 3F1C
BX 0023
CX 0000
A19
DX FCA1
A18 A18 7FFFF 36
: : 7FFFE 25
CS XXXX
A0 A0 7FFFD 19
SS XXXX
: :
DS 2000
D7 D7 : :
ES XXXX
: : 20023 13
D0 D0 20022 7D
BP XXXX
20021 12
SP XXXX
MEMR RD 20020 29
: :
SI XXXX MEMW WR
: :
DI XXXX
00001 95
CS 00000 23
IP XXXX

University of Technology 26
 Partial Decoding

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

80000 1000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

The value of A19 is INSIGNIFICANT to the
memory chip, therefore A19 has no bearing
whether the memory chip will be enabled
University or not 27
of Technology
 Partial Decoding

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

80000 1000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

ACTUAL ADDRESS
University of Technology 28
 Partial Decoding

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

80000 1000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

ACTUAL ADDRESS
University of Technology 29
 Interfacing two 512K Memory Chips to
the 8088 Microprocessor

A19
A18 A18
: :
A0 A0

D7 D7 512KB
: : #2
D0 D0

MEMR RD
MEMW WR
CS
8088
Minimum
Mode
A18
:
A0

D7 512KB
: #1
D0

RD
WR
CS

University of Technology 30
 Interfacing one 512K Memory Chips to
the 8088 Microprocessor

A19
A18 A18
: :
A0 A0

D7 D7
: :
512KB
D0 D0

MEMR RD
MEMW WR
CS
8088
Minimum
Mode

University of Technology 31
 Interfacing one 512K Memory Chips to
the 8088 Microprocessor (version 2)

A19
A18 A18
: :
A0 A0

D7 D7
: :
512KB
D0 D0

MEMR RD
MEMW WR
CS
8088
Minimum
Mode

University of Technology 32
 Interfacing one 512K Memory Chips to
the 8088 Microprocessor (version 3)

A19
A18 A18
: :
A0 A0

D7 D7
: :
512KB
D0 D0

MEMR RD
MEMW WR
CS
8088
Minimum
Mode

University of Technology 33
Interfacing four 256K Memory A17
Chips to :

the 8088 Microprocessor A0

D7
256KB
:
D0 #4
RD
WR
A19
CS
A18
A17 A17
: :
A0 A0
D7 D7
: :
256KB
D0 D0 #3
MEMR RD
MEMW WR

8088 CS
Minimum
A17
Mode :
A0
D7
256KB
:
D0 #2
RD
WR
CS

A17
:
A0
D7
256KB
:
D0 #1
RD
WR
University
CS of Technology 34
Interfacing four 256K Memory A17
Chips to :

the 8088 Microprocessor A0

D7
256KB
:
D0 #4
RD
WR
A19
CS
A18
A17 A17
: :
A0 A0
D7 D7
: :
256KB
D0 D0 #3
MEMR RD
MEMW WR

8088 CS
Minimum
A17
Mode :
A0
D7
256KB
:
D0 #2
RD
WR
CS

A17
:
A0
D7
:
256KB
D0 #1
RD
WR
University
CS of Technology 35
 Memory chip#__ is mapped to:

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

----- ---- ---- ---- ---- ----

----- ---- ---- ---- ---- ----

University of Technology 36
Interfacing four 256K Memory A17
Chips to :

the 8088 Microprocessor A0

D7
256KB
:
D0 #4
RD
WR
A19
CS
A18
A17 A17
: :
A0 A0
D7 D7
: :
256KB
D0 D0 #3
MEMR RD
MEMW WR

8088 CS
Minimum
A17
Mode :
A0
D7
256KB
:
D0 #2
RD
WR
CS

A17
:
A0
D7
:
256KB
D0 #1
RD
WR
University
CS of Technology 37
Interfacing four 256K Memory A17
Chips to :
A0
the 8088 Microprocessor D7
256KB
:
D0 #4
RD
WR
A19
CS
A18
A17 A17
: :
A0 A0
D7 D7
256KB
: :
D0 D0 #3
MEMR RD
MEMW WR

8088 CS
Minimum
A17
Mode :
A0
D7
:
256KB
D0 #2
RD
WR
CS

A17
:
A0
D7
256KB
:
D0 #1
RD
WR
CS
University of Technology 38
Interfacing four 256K Memory A17
Chips to :
A0
the 8088 Microprocessor D7
256KB
:
D0 #4
RD
WR
A19 I1
O3 CS
A18 I0
A17 A17
: :
A0 A0
D7 D7
256KB
: :
D0 D0 #3
MEMR RD
MEMW WR

8088 O2 CS
Minimum
A17
Mode :
A0
D7
:
256KB
D0 #2
RD
WR
O1 CS

A17
:
A0
D7
256KB
:
D0 #1
RD
WR
O0 CS
University of Technology 39
 A12

Interfacing several :
A0
8K Memory Chips to A19
A18
D7
:
8KB
the 8088 P A17 D0 #?
A16 RD
A15 WR
A14
CS
A13
A12

:
:
A0
D7
:

:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
8KB
:
D0 #2
RD
WR
CS

A12
:
A0
D7
:
8KB
D0 #1
RD
WR
CS

University of Technology 40
 A12

Interfacing 128 :
A0
8K Memory Chips to A19
A18
D7
:
8KB
the 8088 P A17 D0 #128
A16 RD
A15 WR
A14
CS
A13
A12

:
:
A0
D7
:

:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
8KB
:
D0 #2
RD
WR
CS

A12
:
A0
D7
:
8KB
D0 #1
RD
WR
CS

University of Technology 41
 A12

Interfacing 128 :
A0
8K Memory Chips to A19 D7
8KB
the 8088 P
A18 :
A17 D0 #128
A16 RD
A15 WR
A14
CS
A13
A12

:
:
A0
D7
:

:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
8KB
:
D0 #2
RD
WR
CS

A12
:
A0
D7
8KB
:
D0 #1
RD
WR
CS

University of Technology 42
 Memory chip#__ is mapped to:

A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 1000

----- ---- ---- ---- ---- ----

----- ---- ---- ---- ---- ----

University of Technology 43
 A12

Interfacing 128 :
A0
8K Memory Chips to A19 D7
8KB
the 8088 P
A18 :
A17 D0 #128
A16 RD
A15 WR
A14
CS
A13
A12

:
:
A0
D7
:

:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
8KB
:
D0 #2
RD
WR
CS

A12
:
A0
D7
8KB
:
D0 #1
RD
WR
CS

University of Technology 44
MEMORY DECODER DESIGN

Address bus
Address
Data cs
Memory 1
Data
24
Address
Address
Bus cs1
CPU 16 Address
Data
Data
Bus Memory 2
cs cs2
Data
WR RD Clk IRQ Reset
cs3

Address
Peripherals
cs
Data

University of Technology 45
• Ngõ vào của address decoder là các đường địa
chỉ cẩn cho giải mã.
• Ngõ ra là các đường Chip select (CS).
• Tại một thời điểm có nhiều nhất một đường CS
tích cực.
• Mức tích cực phụ thuộc vào tính chất của bộ nhớ
hoặc ngoại vi cần giải mã.

University of Technology 46
 Design Step

• Xây dựng bản đồ bộ nhớ (Memory map)

• Thiết lập các hàm cho các đường Chip Select
• Xây dựng Address Decoder bằng các cổng
hoặc bằng các vi mạch LSI như 74LS138,
PAL, GAL, CPLD…

University of Technology 47
 Example

• Thiết kế mạch giải mã địa chỉ cho 2 RAM, có

đường chip select tích cực thấp. Độ rộng
address bus của CPU là 16. Địa chỉ bắt đầu là
0000H
• RAM1: 2K
• RAM2: 4K

University of Technology 48
 Memory map
A15 to AAAA AAAA AAAA AAAA CS
A0 1111 1198 7654 3210
(HEX) 5432 1000

0000H 0000 0000 0000 0000 /CS0 = 0

07FFH 0000 0111 1111 1111
0800H 0000 1000 0000 0000
17FFH 0001 0111 1111 1111 /CS1 = 0

University of Technology 49
A15 to AAAA AAAA AAAA AAAA CS
A0 1111 1198 7654 3210
(HEX) 5432 1000

0000H 0000 0000 0000 0000 /CS0 = 0

07FFH 0000 0111 1111 1111
0000H 0000 0xxx xxxx xxxx /CS0 = 0
07FFH

University of Technology 50
A15 to AAAA AAAA AAAA AAAA CS
A0 1111 1198 7654 3210
(HEX) 5432 1000

0800H 0000 1000 0000 0000

17FFH 0001 0111 1111 1111 /CS1 = 0

0800H 0000 1000 0000 0000

17FFH 0000 1111 1111 1111 /CS1 = 0
0001 0000 0000 0000
0001 0111 1111 1111

0800H 0000 1xxx xxxx xxxx /CS1 = 0

17FFH 0001 0xxx xxxx xxxx

University of Technology 51
A15 to AAAA AAAA AAAA AAAA CS
A0 1111 1198 7654 3210
(HEX) 5432 1000

0000 0xxx xxxx xxxx /CS0 = 0

0000H
07FFH

0800H
17FFH 0000 1xxx xxxx xxxx /CS1 = 0
0001 0xxx xxxx xxxx

University of Technology 52
/ CS 0  A15  A14  A13  A12  A11

/ CS1  ( A15  A14  A13  A12  A11 )( A15  A14  A13  A12  A11 )

University of Technology 53
 THIẾT KẾ DÙNG 74138

Y0
Y 0  G  G 2 A  G 2B  C  B  A
C (MSB)

B Y1 Y1  G  G 2 A  G 2B  C  B  A
A Y2 Y 2  G  G 2 A  G 2B  C  B  A
Y3
Y 3  G  G 2 A  G 2B  C  B  A
Y4
Y 4  G  G 2 A  G 2B  C  B  A
G Y5

G2A Y6 Y 5  G  G 2 A  G 2B  C  B  A
G2B Y7 Y 6  G  G 2 A  G 2B  C  B  A
Y 6  G  G 2 A  G 2B  C  B  A

University of Technology 54
/ CS 0  A15  A14  A13  A12  A11

/ CS1  ( A15  A14  A13  A12  A11 )( A15  A14  A13  A12  A11 )

 A15  A14  ( A13  A12  A11 )( A13  A12  A11 )

University of Technology 55
A13 C (MSB) Y0
CS0 / CS 0  Y 0
A12 B Y1 CS1

A11 A Y2
/ CS1  Y1.Y2
Y3

Y4
/ CS1  Y1.Y2
1
G Y5 / CS 0  A15  A14  A13  A12  A11
A15
G2A Y6
A14 / CS1  ( A15  A14  A13  A12  A11 )( A15  A14  A13  A12  A11 )
G2B Y7
 A15  A14  ( A13  A12  A11 )( A13  A12  A11 )

University of Technology 56