Microprocessors, Microcontrollers

and Embedded Systems

Chapter 12: Interrupts

Introduction
• An interrupt is a hardware-initiated procedure
that interrupts whatever program is currently
executing.
• This chapter provides examples and a
detailed explanation of the interrupt structure
of the entire Intel family of microprocessors.
12–1 BASIC INTERRUPT
PROCESSING
• This section discusses the function of an
interrupt in a microprocessor-based system.
• Structure and features of interrupts available
to Intel microprocessors.
The Purpose of Interrupts
• Interrupts are useful when interfacing I/O
devices at relatively low data transfer rates,
such as keyboard inputs.
• Interrupt processing allows the processor to
execute other software while the keyboard
operator is thinking about what to type next.
• When a key is pressed, the keyboard encoder
debounces the switch and puts out one pulse
that interrupts the microprocessor.
Figure 12–1 A time line that indicates interrupt usage in a typical system.

– a time line shows typing on a keyboard,

a printer removing data from memory,
and a program executing
– the keyboard interrupt service procedure,
called by the keyboard interrupt, and the
printer interrupt service procedure each
take little time to execute
Interrupts
• Intel processors include two hardware pins (INTR
and NMI) that request interrupts…
• And one hardware pin (INTA) to acknowledge the
interrupt requested through INTR.
• The processor also has software interrupts INT,
INTO, INT 3, and BOUND.
• Flag bits IF (interrupt flag) and TF (trap flag), are
also used with the interrupt structure and special
return instruction IRET
– IRETD in the 80386, 80486, or Pentium
Interrupt Vectors
• Interrupt vectors and the vector table are crucial
to an understanding of hardware
and software interrupts.
• The interrupt vector table is located in
the first 1024 bytes of memory at addresses
000000H–0003FFH.
– contains 256 different four-byte interrupt vectors
• An interrupt vector contains the address
(segment and offset) of the interrupt service
procedure.
Figure 12–2 (a) The interrupt vector table for the microprocessor and (b) the contents
of an interrupt vector.

– the first five interrupt vectors are identical

in all Intel processors
– each is four bytes long in real mode and
contains the starting address of the
interrupt service procedure.
– the first two bytes contain the offset address
– the last two contain the segment address
Intel Dedicated Interrupts
• Type 0
The divide error whenever the result from a
division overflows or an attempt is made to
divide by zero.
• Type 2
The non-maskable interrupt occurs when a
logic 1 is placed on the NMI input pin to the
microprocessor.
– non-maskable means it cannot be disabled
• Type 4
Overflow is a special vector used with the
INTO instruction. The INTO instruction
interrupts the program if an overflow
condition exists.
– as reflected by the overflow flag (OF)
• Type 6
An invalid opcode interrupt occurs when
an undefined opcode is encountered in a
program.
• Type 11
The segment not present interrupt occurs
when the protected mode P bit (P = 0) in a
descriptor indicates that the segment is not
present or not valid.
• Type 14
Page fault interrupts occur for any page
fault memory or code access in 80386,
80486, and Pentium–Core2 processors.
Interrupt Instructions: BOUND,
INTO, INT, INT 3, and IRET
• Five software interrupt instructions are
available to the microprocessor:
• INT and INT 3 are very similar.
• BOUND and INTO are conditional.
• IRET is a special interrupt return instruction.
• BOUND has two operands, and compares a
register with two words of memory data.
• INTO checks or tests the overflow flag (O).
– If O = 1, INTO calls the procedure whose
address is stored in interrupt vector type 4
– If O = 0, INTO performs no operation and the
next sequential program instruction executes
• The INT n instruction calls the interrupt
service procedure at the address
represented in vector number n (example int
21h as we did in lab class).
• INT 3 instruction is often used as a
breakpoint-interrupt because it is easy to
insert a one-byte instruction into a program.
– breakpoints are often used to debug software
• The IRET instruction is a special return
instruction used to return for both software
and hardware interrupts.
Operation of a Real Mode Interrupt
• When the processor completes executing the
current instruction, it determines whether an
interrupt is active
• If one or more are present:
– 1. Flag register contents are pushed on the stack
– 2. Interrupt (IF) & trap (TF) flags clear, disabling
the INTR pin.
– 3. Contents of the code segment register (CS)
are pushed onto the stack
– 4. Contents of the instruction pointer (IP) are
pushed onto the stack
– 5. Interrupt vector contents are fetched and
placed into IP and CS so the next instruction
executes at the interrupt service procedure
addressed by the vector
Operation of a Protected Mode
Interrupt
• In protected mode, interrupts have the same
assignments as real mode.
– the interrupt vector table is different
• In place of interrupt vectors, protected mode
uses a set of 256 interrupt descriptors stored
in an interrupt descriptor table (IDT).
• The interrupt descriptor table is located at
any memory location in the system by the
interrupt descriptor table address register
(IDTR).
• Each IDT entry contains the address of the
interrupt service procedure
– in the form of a segment selector and a 32-bit
offset address
– also contains the P bit (present) and DPL bits
to describe the privilege level of the interrupt
12–2 HARDWARE INTERRUPTS
• The two processor hardware interrupt inputs:
– non-maskable interrupt (NMI)
– interrupt request (INTR)
• When NMI input is activated, a type 2
interrupt occurs
– because NMI is internally decoded
• The INTR input must be externally decoded
to select a vector.
• Any interrupt vector can be chosen for the
INTR pin, but we usually use an interrupt
type number between 20H and FFH.
• Intel has reserved interrupts 00H - 1FH for
internal and future expansion.
• INTA is also an interrupt pin on the processor.
– it is an output used in response to INTR input
to apply a vector type number to the data bus
connections D7–D0
• Figure 12–5 shows the three user interrupt
connections on the microprocessor.
Figure 12–5 The interrupt pins on all versions of the Intel microprocessor.
• The non-maskable interrupt (NMI) is an
edge-triggered input that requests an interrupt
on the positive edge (0-to-1 transition).
– after a positive edge, the NMI pin must remain
logic 1 until recognized by the microprocessor
– before the positive edge is recognized, NMI pin
must be logic 0 for at least two clocking periods
• The NMI input is often used for parity errors
and other major faults, such as power failures.
– power failures are easily detected by monitoring
the AC power line and causing an NMI interrupt
whenever AC power drops out
• The processor responds to INTR by pulsing
INTA output in anticipation of receiving an
interrupt vector type number on data bus
connections D7–D0.
• Fig12–9 shows a circuit to apply interrupt
vector type number FFH to the data bus in
response to an INTR.
Figure 12–9 A simple method for generating interrupt vector type number FFH in
response to INTR.
Using a Three-State Buffer for INTA
• Fig 12–10 (see Brey-462p-8th edition) shows how
interrupt vector type number 80H is applied to the
data bus (D0–D7) in response to an INTR.
• In response to INTR, the processor outputs the INTA
to enable a 74ALS244 three-state octal buffer.
• The octal buffer applies the interrupt vector type
number to the data bus in response.
• The vector type number is easily changed with DIP
switches shown in this illustration.
Figure 12–10 A circuit that applies any interrupt vector type number in response to
INTA. Here the circuit is applying type number 80H.
12–3 EXPANDING THE INTERRUPT
STRUCTURE
• This covers three common methods of
expanding the interrupt structure
of the processor.
• It is possible to expand the INTR input so
it accepts seven interrupt inputs.
• Also explained is how to “daisy-chain”
interrupts by software polling.
Using the 74ALS244 to Expand
Interrupts
• The modification shown in Fig 12–13 allows
the circuit of Fig 12–10 to accommodate up to
seven additional interrupt inputs.
• The only hardware change is the addition of
an eight-input NAND gate, which provides the
INTR signal to the microprocessor when any
of the IR inputs becomes active.
Figure 12–13 Expanding the INTR input from one to seven interrupt request lines.
Operation
• If any of the IR inputs becomes logic 0, the
output of the NAND gate goes to logic 1 and
requests an interrupt through the INTR input.
• The interrupt vector that is fetched during the
pulse depends on which interrupt request line
becomes active.
– Table 12–1 shows the interrupt vectors used
by a single interrupt request input
• If two or more interrupt requests are active
active, a new interrupt vector is generated.
Daisy-Chained Interrupt
• Expansion by a daisy-chained interrupt is in
many ways better than using the 74ALS244.
– because it requires only one interrupt vector
• Fig 12–14 shows a two 82C55 peripheral
interfaces with their four INTR outputs daisy-
chained and connected to the single INTR
input of the processor.
• If any interrupt output becomes logic 1, so
does INTR input, causing an interrupt.
Figure 12–14 Two 82C55 PIAs connected to the INTR outputs are daisy-chained to
produce an INTR signal.

– any INTR output from the two

82C55s will cause the INTR
pin on the processor to go
high, requesting an interrupt
– The task of locating which
INTR output became active
is up to the interrupt service
procedure, which must poll
the 82C55s to determine
which output caused the
interrupt
12–4 8259A PROGRAMMABLE
INTERRUPT CONTROLLER
• 8259A (PIC) adds eight vectored priority
encoded interrupts to the microprocessor.
• Expandable, without additional hardware,
to accept up to 64 interrupt requests.
– requires a master 8259A & eight 8259A slaves
• A pair of these controllers still resides and is
programmed as explained here in the latest
chip sets from Intel and other manufacturers.
General Description of the 8259A

– 8259A is easy to connect

to the microprocessor
– all of its pins are direct
connections except the
CS pin, which must be
decoded, and the WR pin,
which must have an I/O
bank write pulse

Figure 12–15 The pin-out of the 8259A programmable interrupt controller (PIC).
8259A Pin-Outs
D0–D7
• The bidirectional data connections are
normally connected to the data bus on the
microprocessor.
IR0–IR7
• Interrupt request inputs are used to request
an interrupt and to connect to a slave in a
system with multiple 8259As.
WR
• The write input connects to write strobe
signal (IOWC) on the microprocessor.

RD
• The read input connects to the IORC signal.

INT
• The interrupt output connects to the INTR
pin on the processor from the master and is
connected to a master IR pin on a slave.
INTA
• Interrupt acknowledge is an input that connects to the
INTA signal on the system.
In a system with a master and slaves, only
the master INTA signal is connected.
CS
• Chip select enables the 8259A for
programming and control.

CAS0–CAS2
• The cascade lines are used as outputs
from the master to the slaves for cascading
multiple 8259As in a system.
SP/EN
• Slave program/enable buffer is a dual-
function pin.

– when the 8259A is in buffered mode, this

output controls the data bus transceivers
in a large microprocessor-based system

– when the 8259A is not in the buffered mode,

this pin programs the device as a master (1)
or a slave (0)