Introduction to FPGA

SAJESH KUMAR U
 Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

Programmable logic device as a black box.

 ROM BASED STRUCTURE

Memory array
N i/o
lines decoder 2N X m bits

M o/p lines
Q1 Q2 Q3 X Q1+ Q2+ Q3+ Z
0 0 0 0 1 0 0 1
0 0 0 1 1 0 1 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
. . . . . . . .
. . . . . . . .
. . . . . . . .
 REALIZATION OF MEALY
MACHINE

z
x D Q1
Q1+
CK
ROM
Q2
D
16x4 Q2+ CK

Q3+ D Q3
CK

CLK
 General structure of a PLA.

x 1 x2 xn

Input buffers
and
inverters

x 1 x1 xn xn

P1

AND plane OR plane

Pk

f1 fm
 Gate-level diagram of a PLA.

x1 x2 x3

Programmable
connections

OR plane
P1

P2

P3

P4

AND plane

f1 f2
 Customary schematic of a PLA

1 2 3

OR plane
P1

P2

P3

P4

AND plane

f1 f2
 An example of a PAL

x1 x2 x3

P1

f1
P2

P3

f2
P4

AND plane
Cypress PAL 22V10
 Structure of a CPLD

I/O block

I/O block
PAL-like PAL-like
block block

Interconnection wires
I/O block

I/O block
PAL-like PAL-like
block block
 A section of a CPLD

PAL-like block (details not shown)

PAL-like block

D Q

D Q

D Q
 Structure of an FPGA.

Logic block Interconnection switches

I/O block

I/O block
I/O block

I/O block
A two-input lookup table (LUT).
 Inclusion of a flip-flop with a LUT

Select

Out
Flip-flop
In1
In2 LUT D Q
In3

Clock
 A section of a programmed FPGA

x3 f

x1

x1 0 x2 0
0 f1 1 f2
0 0
x2 x2 x3
1 0

f1 0
1 f
1
f2
1
 FPGA technologies
 Antifuse
- One Time Programmable technology (OTP)
 SRAM
- Reprogrammable FPGA technology, uses SRAM
configuration cell
 Flash
- Reprogrammable and Nonvolatile FPGA
technology
Comparison of FPGA technologies
Feature SRAM Antifuse Flash
Reprogrammable Yes (ISP) No Yes (ISP)

Programming speed Fast NA > SRAM

Volatile Yes No No

External confign. Yes No No

PROM
Prototyping Yes No Yes

Configuration time Order of 100s of ms Instant on Instant on

Security Poor Very good Very good

Power consumption High Low Medium

Cost High Low Medium

 FPGA Architecture
Programm
able basic
logic cells
(CLBs)

Programmable
IOBs

Programmabl
e interconnect
Typical Logic Cell (Xilinx)
B
G-LUT
SR
G4 Logic
G4
Function of D Q YQ
G3 G1-G4 G3
G CK
G2 G2
EC
G1 G1 H-LUT
SR G4 Logic Y
Function of
H1 H1 F, G, H1 H

DIN F

F4 Logic SR
F4
Function of A D Q XQ
F3 F1-F4
F3
F CK
F2 F2
EC
F1 F1

F-LUT Y
Multiplexer Controlled
by Configuration Program
K

EC
Simplified IOB (Xilinx)
• Fast I/O drivers
DFF/LATCH
D Q
CE

• Registered input, S/R

output,
3-state enable
control D
DFF/LATCH
Q
CE

• Programmable S/R
PAD

slew rate, pull-

up, input delay,
etc. DFF/LATCH
D Q

• Selectable I/O CE

standards
S/R
FPGA DESIGN FLOW
 RTL Design Test Bench

STA
HDL Simulator

Place & Route

Synthesiser

Constraints Tech. Lib.

 Design Entry

 Hardware Description Language (HDL)

 Schematic entry

 Flow chart

 State machine, etc.

 HDL
Industry uses VHDL and Verilog.
Schematic Entry
State Machine
Flow Chart
 Functional Simulation
Check to see if the design functions properly.
 Logic Synthesis

Use an HDL and a logic synthesis tool to

produce a Netlist. Netlist is a description of logic cells
and their interconnections.

Netlist
Synthesis Example
architecture counter_a of counter is
signal q :std_logic_vector(2 downto 0) ;
library ieee; begin
use ieee.std_logic_1164.all; process(clk,rst)
use ieee.std_logic_unsigned.all; begin
entity counter is if (rst='1')then
Port q<="000";
( elsif (clk'event and clk='1') then
clk : in std_logic ; if (q="100")then q<="000";
rst : in std_logic ; else q<=q+'1';
output : out std_logic_vector(2 downto 0) end if;
); end if;
end counter; end process;
output<=q;
end counter_a;
Synthesiser Output
 Floor planning

Arrange the blocks of the Netlist on the chip

Netlist Chip
 Placement

Decide the locations of cells in a block

Chip Block
 Routing

Makes the connection between cells and blocks.

Circuit Extraction

Determine the resistance and capacitance of the

interconnect.

Back-annotated Netlist
 Post Layout Simulation

 Check to see the design still works with added loads of

the interconnect.
 Gate level VHDL / Verilog net list annotated with SDF
FPGA -Xilinx
FPGA Vendors and EDA tools

 FPGAs from Xilinx, Altera, Actel, Lattice

 EDA tools
 Simulation – ModelSim
 Synthesis- Leonardo Spectrum, Precision, Synplify
 P & R- vendor specific
 What is an HDL ?

 HDL - Hardware Description Language

Any language from a class of computer languages for

formal description of electronic circuits. It can describe the
circuit's operation, its design, and tests to verify its
operation by means of simulation.
 HDL’s in demand today

Two standard HDL’s that are supported by IEEE.

 VHDL (Very-High-Speed Integrated Circuit Hardware

Description Language) – Sometimes referred to as VHSIC
HDL, this was developed in early 1980s from an initiative
by US. Dept. of Defense.

 Verilog HDL – developed by Cadence Design Systems

and later transferred to a consortium called Open Verilog
International (OVI).
 Introduction to VHDL

 Defined as an IEEE Standard-1076 in 1987 (Rev.1993, 2002)

 Originally meant for design standardization, documentation,
simulation and ease of maintenance.
 An updated standard IEEE-1164 was later added to introduce
multi-value logic system.

 VHDL, intended for simulation as well as circuit synthesis; not all

constructs defined are synthesizable.

 In 1996, IEEE 1076.3 became a VHDL synthesis standard.

 Why VHDL?
 Public availability
 Technology and target independence
 Reduced Time to Market
 Design methodology & Modeling
 Large scale design
VHDL model of an AND gate
Library ieee;
Use ieee.std_logic_1164.all;
entity my_and is
port (a : in std_logic;
b : in std_logic;
c: out std_logic);
end my_and;

architecture my_and_beh of my_and is

begin
process (a,b)
begin
if (a=‘1’ and b=‘1’) then
c<=‘1’;
else
c<=‘0’;
end if;
end process;
end my_and_beh;
 Primary Design Units

 Entity - Specifies the interface of the underlying design

with the external world. It basically defines the IO’s of the
system.

 Architecture - Describes a design’s behavior and

functionality. It has no existence without an entity.
 Primary Design Units (contd..)

 Configuration - Binds an entity to an architecture when

there are multiple architectures for a single entity.

 Package - Contains frequently used declarations,

constants, functions, procedures, user defined data types
and components.

 Library - Consists of all compiled design units like

entities, architectures, packages and configurations.
 VHDL Code Structure
LIBRARY Declarations

Basic VHDL
ENTITY
Code Structure

Architecture

 Library – A collection of commonly used pieces of

code. Placing them in the code allows a design to
be reused.
 Parts of a library
LIBRARY

PACKAGE

FUNCTIONS
PROCEDURES
COMPONENTS
CONSTANTS
TYPES
 Entity
 Entity defines a new component, its IO connections
and related declarations.

 It can be used as a component after being compiled

into a library.

 Any data type used in an entity must be previously

declared in a standard or user defined package.
 Entity declaration
_____Syntax_________________________________
entity entity_name is
port port_name : port direction data_type
end entity_name ;

_____example________________________________
entity my_and is
port ( a : in std_logic; -- Input Port
b : in std_logic; -- Input Port
c : out std_logic); -- Output Port
end my_and;
 Architecture
 Architecture specifies the behavior, function, interconnection and the

relationship between the inputs and outputs of an entity.

 Architectures can have various levels of abstraction and

implementations.

 An entity can have more than one architecture.

 When multiple architectures are defined, then each is bound to an

entity using configuration statement.

 Architecture (contd..)
________Syntax_____________________________
architecture architecture_name of entity_name is
signal declarations;
component declarations;
begin
statement1;
statement2;
…………..
…………..
end architecture_name;
 Architecture classification
 Behavioral - sequentially described functioning of the
design
 Structural - interconnection of previously defined
components

 Dataflow - flow of data through the design is expressed

using concurrent signal assignment statements.

Possible to have a mix of all three modeling styles

________Behavioral Style__________________________________
entity my_and is
port (a : in std_logic;
b : in std_logic;
c: out std_logic);
end my_and;

architecture my_and_beh of my_and is

begin
process (a,b)
begin
if (a=‘1’ and b=‘1’) then
c<=‘1’;
else
c<=‘0’;
end if;
end process;
end my_and_beh;
________Structural Style_______________________________

entity my_and is
port ( a : in std_logic;
b : in std_logic;
c: out std_logic);
end my_and;

architecture my_and_struct of my_and is

component AND2
port ( x: in std_logic;
y: in std_logic;
z: out std_logic);
end component;

begin
u0:AND2 port map (x => a, y => b, z=> c);

end my_and_struct;
___Data flow Style____________________________

entity my_and is
port ( a : in std_logic;
b : in std_logic;
c: out std_logic);
end my_and;

architecture my_and_data of my_and is

begin

c <= a and b;

end my_and_data;
 Configuration

 Used to select one of the possibly many architecture

bodies that an entity may have.
 Configuration saves re-compile time when some
components need substitution in a large design.
 The synthesiser ignores configuration.
__________Example______________________________________

configuration THREE of FULLADDER is

for STRUCTURAL
for INST_HA1, INST_HA2: HA
use entity WORK.HALFADDER(CONCURRENT);
end for;
for INST_XOR: XOR
use entity WORK.XOR2D1(CONCURRENT);
end for;
end for;
end THREE;
 Library
 Collection of compiled VHDL design units.

 Promotes sharing of compiled design and hides

source code from the users.

 WORK and STD are the default libraries provided by

the language. They need not be explicitly declared.
 Commonly used functions, procedures and user data
types can be compiled into a user defined library for
use in all designs.
Library (contd..)
______example_____________________________

library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_1164_unsigned.all ;
library my_library ;
use my_library.my_package.all ;
 Package
 A package is a collection of commonly used
subprograms, data types and constants.
 Package promotes code reuse.
 STANDARD and TEXTIO are provided in the STD
library that defines useful data types and utilities.
 ‘USE’ statement is used to access components
inside a library.
 Package (contd..)
Package consists of two parts-
Package Header - defines the contents of a package
that is made visible after the statement.
“use library.package_name.all”.

Package body - provides the implementation details of

sub programs. Items declared in the body are not visible
to the user of the package.
______Example : Package with a function___________

package my_package is
type state is (st1 st2, st3, st4);
constant vec : std_logic_vector(7 downto 0) := “11110000”;
function positive_edge (signal s: std_logic) return boolean;
end my_package;

package body my_package is

function positive_edge (signal s: std_logic) return boolean is
begin
return (s’event and s=‘1’);
end positive_edge;
end my_package;
 Basic Language elements
• Class
• Objects
• Data types
• Operators

class object data type

signal a : std_logic
 Class
• Class types: Constant, Variable, Signal
– Constant
 can be declared in all parts of a program
 can be of any type
 used to make the code more readable
constant a : std_logic_vector :=“1010”
– Variable
• Identifier used in a process or a subprogram for local
data storage
• have only type and value attached, no past history
variable j : integer range 0 to 10;
 Class
– Signal
• connects design entities together and communicates
changes in values.

• can be declared in an entity, architecture, package, as a

parameter of a subprogram
• have type and type attributes, value and time (i.e. it has a
history).
• signal assignment is concurrent outside the process and
sequential inside the process.
 Class
• Signals take last value assigned to it in a process and are

assigned the value only after the completion of the simulation

cycle run.

• Signal updates can have a delay specified in their assignment

statements.
signal clk : std_logic;

clk <= not clk after 10 ns;

 Data types

• Each identifier must have a data type which

determines the value, it can assume.
• VHDL supports a variety of data types.
• Users can define their own data types and
operators in user defined packages.
 Some Data types
• Character
e.g. ‘a’, ‘A’, ‘1’, ’#’ ,“warning”, “setup time violation”
• Boolean - can only be true or false.
• Integer
• Real
• Physical
• Bit
• Std_logic- 9 valued logic defined in std_logic_1164 package
• Enumerated- for user defined values

e.g. type instruction is (add, sub, mul, div);

Operators

• Logical operators: and, or, nand, nor, xor, xnor, not.

• Relational operators: =, /=, <, <=, >, >=
• Shift operators: rol, ror, …
• Arithmetic operators: +, -, *, …
VHDL Model of a Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
Port
(
clk : in std_logic ;
rst : in std_logic ;
output : out std_logic_vector(2 downto 0)
);
end counter;

architecture counter_a of counter is

signal q :std_logic_vector(2 downto 0) ;
begin
process(clk,rst)
begin
if (rst='1')then
q<="000";
elsif (clk'event and clk='1') then
if (q="100")then q<="000";
else q<=q+'1';
end if;
end if;
end process;
output<=q;
end counter_a;
 Concurrent Statements
• All concurrent statements in an architecture are
executed simultaneously.
• Concurrent statements are used to express parallel
activity.
• The order in which concurrent statements are written
does not have any effect on their functionality.
• Process is the only concurrent statement in which
sequential statements are allowed.
• There can be more than one process in an architecture.
• All the processes in an architecture are executed
simultaneously.
 Concurrency in VHDL

• All concurrent statements in VHDL execute simultaneously

architecture example of ex is
begin
a <= b; b <= c;
b <= c; both are same a <= b;
end;
 The simulator executes concurrent statements when one of the
signals in the sensitivity list changes. This is called occurrence of an
event.
Conditional signal assignment
• The when statement has one target but multiple expressions.
• Assigns value based on the priority of the condition.

______example___________________________
entity my_ex is
port ( a,b,c : in std_logic;
data : in std_logic_vector(1 downto 0);
q : out std_logic);
end my_ex;
architecture my_ex_a of my_ex is
begin
q <= a when data=“00” else
b when data=“11” else
c;
end my_ex_a;
 Selective Signal Assignment

• Using with statement a target signal can assign

different values according to the value of an another
signal
• Unlike when statement with statement does not have
any priority.
• Each statement in the with statement should be
unique.
_____example______________________________
entity my_ex is
port ( a, b, c : in std_logic;
data : in std_logic_vector(1 downto 0);
q : out std_logic);
end my_ex;

architecture my_ex_a of my_ex is

begin
with data select
q <= a when “00”,
b when “11”,
c when others;
end my_ex_a;
 The process statement
 The process statement defines the behavior of the design.

 The order of execution of statements inside the process is the order

in which the statements are written.

 On an event on any of the signals in sensitivity list, all the

statements in the process are executed.

_____syntax_________________________________
process (sensitivity list)
declarations;
begin
sequential statements;
end process;
 Sequential statement

• Statements that are analysed serially one after the other.

• The final output depends on the order of the statements.
• Allowed only inside the process or in a subprogram.

• The process is the primary statement which describes sequential

behavior of an entity.

• There can be two types of process statements - Combinational

process and Clocked process
 Combinational process

• Generates purely combinational logic

• All the inputs must be present in the sensitivity list.

____________example_______________________

process (a, b, c)
begin
d <= (a and b) or c ;
end process;
 Clocked process

• Generates sequential logic.

• Clocked process should have only clk and other asynchronous

inputs in the sensitivity list to improve simulation speed.

_____example____________________________________
process(clk, rst)
begin
if rst = ‘1’ then
q <= ‘0’ elsif( clk’event and clk = ‘1’ then)
q <= d;
end if;
end process;
 The if statement
• An if statement selects one or more of a sequence of
events to execute depending on a condition.
• If statement can be nested.
• If statement generates a priority structure.
• If corresponds to when statement in the concurrent
part.
____example____________________

If reset =‘1’ then

count <= “000”
elsif (clk’event and clk=‘1’)then
count <= count +’1’ ;
end if ;
 The Case Statement

• The case statement selects one of a number of alternative

sequences of statements for execution.
• Corresponds to with-select statement in the concurrent part.
• Does not result in prioritized logic unlike the if statement.
• The choices for case statement must not overlap.

i.e. each choice of the expression must be covered in one

and only one when clause.
____example____________________________
case sel is
when “00”=>
dout <= a;
when “01”=>
dout <= b;
when “10”=>
dout <= c;
when others=>
dout <= d;
end case;
 Structural VHDL
• Interconnection of a number of components
• Helps hierarchical design of complex circuits

• The component has to be declared in either a package or in the

declaration part of the architecture prior to its instantiation.
architecture my_and_struct of my_and is

component AND2
port ( x: in std_logic;
y: in std_logic;
z: out std_logic);
end component;

begin
u0:AND2 port map (x => a, y => b, z=> c);

end my_and_struct;
 Delays in VHDL

• There are two types of delays in VHDL

– Inertial delay
– Transport delay
 Inertial delay

• It’s the default delay in VHDL.

• It’s used to model component delays.
• Spikes are not propagated.
• The reject command rejects spikes of duration less than
the specified time.
 ____example__________________________
B <= A inertial after 10 ns;
0 10 20 30 40 50 60 70 80

B <= inertial A after 10 ns;

B <= reject 4 ns inertial A after 10 ns;

 Transport delay

• Its used for modeling interconnect delays.

• Spikes are propagated irrespective of its width.

• Uses the keyword transport.

e.g.. C <= A and B transport after 5 ns;

 ____example____________________________
B <= A transport after 10 ns;
0 10 20 30 40 50 60 70 80

B<= transport A after 10 ns

 Review Questions

Primary design units in VHDL?

An entity can have only one architecture?
A process statement always models sequential
logic?
The order in which concurrent statements are
written effects the functionality ?