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authorThomas Munro2022-07-07 23:21:46 +0000
committerThomas Munro2022-07-08 02:14:57 +0000
commit0ad5b48e58945e88b71eb5932d0c003a95def6ea (patch)
tree1013071c1b62e8c867a908ac4fd97d9ca815cce8 /src/include/port/atomics
parent9db300ce6e38411144f1e36dba345a5f91bbdee4 (diff)
Remove HP/Intel Itanium support.
This CPU architecture has been discontinued. We already removed HP-UX support, we never supported Windows/Itanium, and the open source operating systems that a vintage hardware owner might hope to run have all either ended Itanium support or never fully released support (NetBSD may eventually). The extra code we carry for this rare ISA is now untested. It seems like a good time to remove it. Reviewed-by: Tom Lane <[email protected]> Reviewed-by: Andres Freund <[email protected]> Discussion: https://postgr.es/m/1415825.1656893299%40sss.pgh.pa.us
Diffstat (limited to 'src/include/port/atomics')
-rw-r--r--src/include/port/atomics/arch-ia64.h27
-rw-r--r--src/include/port/atomics/generic-msvc.h2
2 files changed, 1 insertions, 28 deletions
diff --git a/src/include/port/atomics/arch-ia64.h b/src/include/port/atomics/arch-ia64.h
deleted file mode 100644
index 264d2316b97..00000000000
--- a/src/include/port/atomics/arch-ia64.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*-------------------------------------------------------------------------
- *
- * arch-ia64.h
- * Atomic operations considerations specific to intel itanium
- *
- * Portions Copyright (c) 1996-2022, PostgreSQL Global Development Group
- * Portions Copyright (c) 1994, Regents of the University of California
- *
- * NOTES:
- *
- * src/include/port/atomics/arch-ia64.h
- *
- *-------------------------------------------------------------------------
- */
-
-/*
- * Itanium is weakly ordered, so read and write barriers require a full
- * fence.
- */
-#if defined(__INTEL_COMPILER)
-# define pg_memory_barrier_impl() __mf()
-#elif defined(__GNUC__)
-# define pg_memory_barrier_impl() __asm__ __volatile__ ("mf" : : : "memory")
-#endif
-
-/* per architecture manual doubleword accesses have single copy atomicity */
-#define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY
diff --git a/src/include/port/atomics/generic-msvc.h b/src/include/port/atomics/generic-msvc.h
index 6294162b4cc..1a4adfde686 100644
--- a/src/include/port/atomics/generic-msvc.h
+++ b/src/include/port/atomics/generic-msvc.h
@@ -86,7 +86,7 @@ pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
return ret;
}
-/* Only implemented on itanium and 64bit builds */
+/* Only implemented on 64bit builds */
#ifdef _WIN64
#pragma intrinsic(_InterlockedExchangeAdd64)