#include "Target/ARM/ARMSubtarget.h"

Inheritance diagram for llvm::ARMSubtarget:

Public Types
enum	ARMLdStMultipleTiming { DoubleIssue , DoubleIssueCheckUnalignedAccess , SingleIssue , SingleIssuePlusExtras }
	What kind of timing do load multiple/store multiple instructions have. More...
enum	PushPopSplitVariation { NoSplit , SplitR7 , SplitR11WindowsSEH , SplitR11AAPCSSignRA }
	How the push and pop instructions of callee saved general-purpose registers should be split. More...

Public Member Functions
	ARMSubtarget (const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
	This constructor initializes the data members to match that of the specified triple.
unsigned	getMaxInlineSizeThreshold () const
	getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
unsigned	getMaxMemcpyTPInlineSizeThreshold () const
	getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline a llvm.memcpy as a Tail Predicated loop.
void	ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
	ParseSubtargetFeatures - Parses features string setting specified subtarget options.
ARMSubtarget &	initializeSubtargetDependencies (StringRef CPU, StringRef FS)
	initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.
const ARMSelectionDAGInfo *	getSelectionDAGInfo () const override
const ARMBaseInstrInfo *	getInstrInfo () const override
const ARMTargetLowering *	getTargetLowering () const override
const ARMFrameLowering *	getFrameLowering () const override
const ARMBaseRegisterInfo *	getRegisterInfo () const override
const CallLowering *	getCallLowering () const override
InstructionSelector *	getInstructionSelector () const override
const LegalizerInfo *	getLegalizerInfo () const override
const RegisterBankInfo *	getRegBankInfo () const override
bool	hasARMOps () const
bool	useNEONForSinglePrecisionFP () const
bool	hasVFP2Base () const
bool	hasVFP3Base () const
bool	hasVFP4Base () const
bool	hasFPARMv8Base () const
bool	hasAnyDataBarrier () const
bool	useMulOps () const
bool	useFPVMLx () const
bool	useFPVFMx () const
bool	useFPVFMx16 () const
bool	useFPVFMx64 () const
bool	hasBaseDSP () const
bool	hasFusion () const
	Return true if the CPU supports any kind of instruction fusion.
const Triple &	getTargetTriple () const
bool	isReadTPSoft () const
bool	isTargetAndroid () const
bool	isXRaySupported () const override
bool	isROPI () const
bool	isRWPI () const
bool	useMachineScheduler () const
bool	useMachinePipeliner () const
bool	hasMinSize () const
bool	isThumb1Only () const
bool	isThumb2 () const
bool	isMClass () const
bool	isRClass () const
bool	isAClass () const
bool	isR9Reserved () const
MCPhysReg	getFramePointerReg () const
enum PushPopSplitVariation	getPushPopSplitVariation (const MachineFunction &MF) const
bool	useStride4VFPs () const
bool	useMovt () const
bool	supportsTailCall () const
bool	allowsUnalignedMem () const
bool	restrictIT () const
const std::string &	getCPUString () const
bool	isLittle () const
unsigned	getMispredictionPenalty () const
bool	enableMachineScheduler () const override
	Returns true if machine scheduler should be enabled.
bool	enableMachinePipeliner () const override
	Returns true if machine pipeliner should be enabled.
bool	useDFAforSMS () const override
bool	enablePostRAScheduler () const override
	True for some subtargets at > -O0.
bool	enablePostRAMachineScheduler () const override
	True for some subtargets at > -O0.
bool	enableSubRegLiveness () const override
	Check whether this subtarget wants to use subregister liveness.
bool	useAA () const override
	Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
const InstrItineraryData *	getInstrItineraryData () const override
	getInstrItins - Return the instruction itineraries based on subtarget selection.
Align	getStackAlignment () const
	getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.
Align	getDualLoadStoreAlignment () const
unsigned	getMaxInterleaveFactor () const
unsigned	getPartialUpdateClearance () const
ARMLdStMultipleTiming	getLdStMultipleTiming () const
int	getPreISelOperandLatencyAdjustment () const
bool	isGVIndirectSymbol (const GlobalValue *GV) const
	True if the GV will be accessed via an indirect symbol.
bool	isGVInGOT (const GlobalValue *GV) const
	Returns the constant pool modifier needed to access the GV.
bool	useFastISel () const
	True if fast-isel is used.
unsigned	getReturnOpcode () const
	Returns the correct return opcode for the current feature set.
bool	allowPositionIndependentMovt () const
	Allow movt+movw for PIC global address calculation.
unsigned	getPreferBranchLogAlignment () const
unsigned	getMVEVectorCostFactor (TargetTransformInfo::TargetCostKind CostKind) const
bool	ignoreCSRForAllocationOrder (const MachineFunction &MF, MCRegister PhysReg) const override
unsigned	getGPRAllocationOrder (const MachineFunction &MF) const

bool	isCortexA5 () const
bool	isCortexA7 () const
bool	isCortexA8 () const
bool	isCortexA9 () const
bool	isCortexA15 () const
bool	isSwift () const
bool	isCortexM3 () const
bool	isCortexM55 () const
bool	isCortexM7 () const
bool	isCortexM85 () const
bool	isLikeA9 () const
bool	isCortexR5 () const
bool	isKrait () const

bool	isTargetDarwin () const
bool	isTargetIOS () const
bool	isTargetWatchOS () const
bool	isTargetWatchABI () const
bool	isTargetDriverKit () const
bool	isTargetLinux () const
bool	isTargetNetBSD () const
bool	isTargetWindows () const
bool	isTargetCOFF () const
bool	isTargetELF () const
bool	isTargetMachO () const
bool	isTargetAEABI () const
bool	isTargetGNUAEABI () const
bool	isTargetMuslAEABI () const
bool	isTargetEHABICompatible () const

Protected Types
enum	ARMProcFamilyEnum { Others }
enum	ARMProcClassEnum { None , AClass , MClass , RClass }
enum	ARMArchEnum

Protected Attributes
ARMProcFamilyEnum	ARMProcFamily = Others
	ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
ARMProcClassEnum	ARMProcClass = None
	ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
ARMArchEnum	ARMArch = ARMv4t
	ARMArch - ARM architecture.
bool	UseMulOps = false
	UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.
bool	SupportsTailCall = false
	SupportsTailCall - True if the OS supports tail call.
bool	RestrictIT = false
	RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Align	stackAlignment = Align(4)
	stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.
std::string	CPUString
	CPUString - String name of used CPU.
unsigned	MaxInterleaveFactor = 1
unsigned	PartialUpdateClearance = 0
	Clearance before partial register updates (in number of instructions)
ARMLdStMultipleTiming	LdStMultipleTiming = SingleIssue
	What kind of timing do load multiple/store multiple have (double issue, single issue etc).
int	PreISelOperandLatencyAdjustment = 2
	The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands.
unsigned	PreferBranchLogAlignment = 0
	What alignment is preferred for loop bodies and functions, in log2(bytes).
unsigned	MVEVectorCostFactor = 0
	The cost factor for MVE instructions, representing the multiple beats an.
bool	OptMinSize = false
	OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
bool	IsLittle
	IsLittle - The target is Little Endian.
Triple	TargetTriple
	TargetTriple - What processor and OS we're targeting.
MCSchedModel	SchedModel
	SchedModel - Processor specific instruction costs.
InstrItineraryData	InstrItins
	Selected instruction itineraries (one entry per itinerary class.)
const TargetOptions &	Options
	Options passed via command line that could influence the target.
const ARMBaseTargetMachine &	TM

Detailed Description

Definition at line 48 of file ARMSubtarget.h.

Member Enumeration Documentation

◆ ARMArchEnum

enum llvm::ARMSubtarget::ARMArchEnum

protected

Definition at line 63 of file ARMSubtarget.h.

◆ ARMLdStMultipleTiming

enum llvm::ARMSubtarget::ARMLdStMultipleTiming

What kind of timing do load multiple/store multiple instructions have.

Enumerator
DoubleIssue	Can load/store 2 registers/cycle.
DoubleIssueCheckUnalignedAccess	Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
SingleIssue	Can load/store 1 register/cycle.
SingleIssuePlusExtras	Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially also for register writeback.

Definition at line 71 of file ARMSubtarget.h.

◆ ARMProcClassEnum

enum llvm::ARMSubtarget::ARMProcClassEnum

protected

Enumerator
None
AClass
MClass
RClass

Definition at line 56 of file ARMSubtarget.h.

◆ ARMProcFamilyEnum

enum llvm::ARMSubtarget::ARMProcFamilyEnum

protected

Enumerator
Others

Definition at line 50 of file ARMSubtarget.h.

◆ PushPopSplitVariation

enum llvm::ARMSubtarget::PushPopSplitVariation

How the push and pop instructions of callee saved general-purpose registers should be split.

Enumerator
NoSplit	All GPRs can be pushed in a single instruction. push {r0-r12, lr} vpush {d8-d15}
SplitR7	R7 and LR must be adjacent, because R7 is the frame pointer, and must point to a frame record consisting of the previous frame pointer and the return address. push {r0-r7, lr} push {r8-r12} vpush {d8-d15} Note that Thumb1 changes this layout when the frame pointer is R11, using a longer sequence of instructions because R11 can't be used by a Thumb1 push instruction. This doesn't currently have a separate enum value, and is handled entriely within Thumb1FrameLowering::emitPrologue.
SplitR11WindowsSEH	When the stack frame size is not known (because of variable-sized objects or realignment), Windows SEH requires the callee-saved registers to be stored in three regions, with R11 and LR below the floating-point registers. push {r0-r10, r12} vpush {d8-d15} push {r11, lr}
SplitR11AAPCSSignRA	When generating AAPCS-compilant frame chains, R11 is the frame pointer, and must be pushed adjacent to the return address (LR). Normally this isn't a problem, because the only register between them is r12, which is the intra-procedure-call scratch register, so doesn't need to be saved. However, when PACBTI is in use, r12 contains the authentication code, so does need to be saved. This means that we need a separate push for R11 and LR. push {r0-r10, r12} push {r11, lr} vpush {d8-d15}

Definition at line 86 of file ARMSubtarget.h.

Constructor & Destructor Documentation

◆ ARMSubtarget()

ARMSubtarget::ARMSubtarget	(	const Triple &	TT,
		const std::string &	CPU,
		const std::string &	FS,
		const ARMBaseTargetMachine &	TM,
		bool	IsLittle,
		bool	MinSize = false )

This constructor initializes the data members to match that of the specified triple.

Definition at line 88 of file ARMSubtarget.cpp.

References CPUString, llvm::createARMInstructionSelector(), getRegisterInfo(), getTargetLowering(), IsLittle, isThumb(), isThumb1Only(), Options, OptMinSize, TargetTriple, TM, UseFusedMulOps, and UseMulOps.

Referenced by initializeSubtargetDependencies(), and ParseSubtargetFeatures().

Member Function Documentation

◆ allowPositionIndependentMovt()

bool llvm::ARMSubtarget::allowPositionIndependentMovt ( ) const

inline

Allow movt+movw for PIC global address calculation.

ELF does not have GOT relocations for movt+movw. ROPI does not use GOT.

Definition at line 482 of file ARMSubtarget.h.

References isROPI(), and isTargetELF().

◆ allowsUnalignedMem()

bool llvm::ARMSubtarget::allowsUnalignedMem ( ) const

inline

Definition at line 401 of file ARMSubtarget.h.

Referenced by getDualLoadStoreAlignment().

◆ enableMachinePipeliner()

bool ARMSubtarget::enableMachinePipeliner ( ) const

override

Returns true if machine pipeliner should be enabled.

Definition at line 359 of file ARMSubtarget.cpp.

References useMachinePipeliner().

Referenced by llvm::ARMBaseInstrInfo::analyzeBranch().

◆ enableMachineScheduler()

bool ARMSubtarget::enableMachineScheduler ( ) const

override

Returns true if machine scheduler should be enabled.

Definition at line 340 of file ARMSubtarget.cpp.

References hasMinSize(), isMClass(), and useMachineScheduler().

Referenced by enablePostRAMachineScheduler(), and enablePostRAScheduler().

◆ enablePostRAMachineScheduler()

bool ARMSubtarget::enablePostRAMachineScheduler ( ) const

override

True for some subtargets at > -O0.

Definition at line 377 of file ARMSubtarget.cpp.

References enableMachineScheduler(), and isThumb1Only().

◆ enablePostRAScheduler()

bool ARMSubtarget::enablePostRAScheduler ( ) const

override

True for some subtargets at > -O0.

Definition at line 368 of file ARMSubtarget.cpp.

References enableMachineScheduler(), and isThumb1Only().

◆ enableSubRegLiveness()

bool ARMSubtarget::enableSubRegLiveness ( ) const

override

Check whether this subtarget wants to use subregister liveness.

Definition at line 353 of file ARMSubtarget.cpp.

◆ getCallLowering()

const CallLowering * ARMSubtarget::getCallLowering ( ) const

override

Definition at line 118 of file ARMSubtarget.cpp.

◆ getCPUString()

const std::string & llvm::ARMSubtarget::getCPUString ( ) const

inline

Definition at line 405 of file ARMSubtarget.h.

References CPUString.

◆ getDualLoadStoreAlignment()

Align llvm::ARMSubtarget::getDualLoadStoreAlignment ( ) const

inline

Definition at line 443 of file ARMSubtarget.h.

References allowsUnalignedMem().

Referenced by LowerSTORE().

◆ getFrameLowering()

const ARMFrameLowering * llvm::ARMSubtarget::getFrameLowering ( ) const

inlineoverride

Definition at line 243 of file ARMSubtarget.h.

Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex().

◆ getFramePointerReg()

MCPhysReg llvm::ARMSubtarget::getFramePointerReg ( ) const

inline

Definition at line 385 of file ARMSubtarget.h.

References isTargetDarwin(), isTargetWindows(), and isThumb().

Referenced by llvm::ARMBaseRegisterInfo::canRealignStack(), llvm::ARMAsmPrinter::emitInstruction(), llvm::ARMBaseRegisterInfo::getFrameRegister(), getPushPopSplitVariation(), llvm::ARMBaseRegisterInfo::getReservedRegs(), and llvm::ARMBaseRegisterInfo::isInlineAsmReadOnlyReg().

◆ getGPRAllocationOrder()

unsigned ARMSubtarget::getGPRAllocationOrder ( const MachineFunction & MF ) const

Definition at line 415 of file ARMSubtarget.cpp.

References llvm::MachineFunction::getFunction(), llvm::Function::hasMinSize(), isThumb1Only(), and isThumb2().

◆ getInstrInfo()

const ARMBaseInstrInfo * llvm::ARMSubtarget::getInstrInfo ( ) const

inlineoverride

Definition at line 235 of file ARMSubtarget.h.

Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex(), emitThumb1LoadConstPool(), llvm::ARMCallLowering::lowerCall(), and llvm::ThumbRegisterInfo::resolveFrameIndex().

◆ getInstrItineraryData()

const InstrItineraryData * llvm::ARMSubtarget::getInstrItineraryData ( ) const

inlineoverride

getInstrItins - Return the instruction itineraries based on subtarget selection.

Definition at line 433 of file ARMSubtarget.h.

References InstrItins.

◆ getInstructionSelector()

InstructionSelector * ARMSubtarget::getInstructionSelector ( ) const

override

Definition at line 122 of file ARMSubtarget.cpp.

◆ getLdStMultipleTiming()

ARMLdStMultipleTiming llvm::ARMSubtarget::getLdStMultipleTiming ( ) const

inline

Definition at line 451 of file ARMSubtarget.h.

References LdStMultipleTiming.

◆ getLegalizerInfo()

const LegalizerInfo * ARMSubtarget::getLegalizerInfo ( ) const

override

Definition at line 126 of file ARMSubtarget.cpp.

◆ getMaxInlineSizeThreshold()

unsigned llvm::ARMSubtarget::getMaxInlineSizeThreshold ( ) const

inline

getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.

Definition at line 213 of file ARMSubtarget.h.

Referenced by llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), and shouldGenerateInlineTPLoop().

◆ getMaxInterleaveFactor()

unsigned llvm::ARMSubtarget::getMaxInterleaveFactor ( ) const

inline

Definition at line 447 of file ARMSubtarget.h.

References MaxInterleaveFactor.

◆ getMaxMemcpyTPInlineSizeThreshold()

unsigned llvm::ARMSubtarget::getMaxMemcpyTPInlineSizeThreshold ( ) const

inline

getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline a llvm.memcpy as a Tail Predicated loop.

This threshold should only be used for constant size inputs.

Definition at line 221 of file ARMSubtarget.h.

Referenced by shouldGenerateInlineTPLoop().

◆ getMispredictionPenalty()

unsigned ARMSubtarget::getMispredictionPenalty ( ) const

Definition at line 336 of file ARMSubtarget.cpp.

References SchedModel.

◆ getMVEVectorCostFactor()

unsigned llvm::ARMSubtarget::getMVEVectorCostFactor ( TargetTransformInfo::TargetCostKind CostKind ) const

inline

Definition at line 491 of file ARMSubtarget.h.

References CostKind, MVEVectorCostFactor, and llvm::TargetTransformInfo::TCK_CodeSize.

◆ getPartialUpdateClearance()

unsigned llvm::ARMSubtarget::getPartialUpdateClearance ( ) const

inline

Definition at line 449 of file ARMSubtarget.h.

References PartialUpdateClearance.

◆ getPreferBranchLogAlignment()

unsigned llvm::ARMSubtarget::getPreferBranchLogAlignment ( ) const

inline

Definition at line 486 of file ARMSubtarget.h.

References PreferBranchLogAlignment.

◆ getPreISelOperandLatencyAdjustment()

int llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment ( ) const

inline

Definition at line 455 of file ARMSubtarget.h.

References PreISelOperandLatencyAdjustment.

◆ getPushPopSplitVariation()

ARMSubtarget::PushPopSplitVariation ARMSubtarget::getPushPopSplitVariation ( const MachineFunction & MF ) const

◆ getRegBankInfo()

const RegisterBankInfo * ARMSubtarget::getRegBankInfo ( ) const

override

Definition at line 130 of file ARMSubtarget.cpp.

Referenced by llvm::ARMCallLowering::lowerCall().

◆ getRegisterInfo()

const ARMBaseRegisterInfo * llvm::ARMSubtarget::getRegisterInfo ( ) const

inlineoverride

Definition at line 247 of file ARMSubtarget.h.

Referenced by ARMSubtarget(), llvm::Thumb1InstrInfo::copyPhysReg(), getPushPopSplitVariation(), insertSEH(), and llvm::ARMCallLowering::lowerCall().

◆ getReturnOpcode()

unsigned llvm::ARMSubtarget::getReturnOpcode ( ) const

inline

Returns the correct return opcode for the current feature set.

Use BX if available to allow mixing thumb/arm code, but fall back to plain mov pc,lr on ARMv4.

Definition at line 471 of file ARMSubtarget.h.

References isThumb().

◆ getSelectionDAGInfo()

const ARMSelectionDAGInfo * llvm::ARMSubtarget::getSelectionDAGInfo ( ) const

inlineoverride

Definition at line 231 of file ARMSubtarget.h.

◆ getStackAlignment()

Align llvm::ARMSubtarget::getStackAlignment ( ) const

inline

getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.

Definition at line 440 of file ARMSubtarget.h.

References stackAlignment.

◆ getTargetLowering()

const ARMTargetLowering * llvm::ARMSubtarget::getTargetLowering ( ) const

inlineoverride

Definition at line 239 of file ARMSubtarget.h.

Referenced by AlignBlocks(), ARMSubtarget(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), and PerformXORCombine().

◆ getTargetTriple()

const Triple & llvm::ARMSubtarget::getTargetTriple ( ) const

inline

Definition at line 330 of file ARMSubtarget.h.

References TargetTriple.

◆ hasAnyDataBarrier()

bool llvm::ARMSubtarget::hasAnyDataBarrier ( ) const

inline

Definition at line 309 of file ARMSubtarget.h.

References isThumb().

◆ hasARMOps()

bool llvm::ARMSubtarget::hasARMOps ( ) const

inline

Definition at line 298 of file ARMSubtarget.h.

Referenced by isXRaySupported().

◆ hasBaseDSP()

bool llvm::ARMSubtarget::hasBaseDSP ( ) const

inline

Definition at line 320 of file ARMSubtarget.h.

References isThumb().

Referenced by AddCombineTo64BitSMLAL16().

◆ hasFPARMv8Base()

bool llvm::ARMSubtarget::hasFPARMv8Base ( ) const

inline

Definition at line 307 of file ARMSubtarget.h.

◆ hasFusion()

bool llvm::ARMSubtarget::hasFusion ( ) const

inline

Return true if the CPU supports any kind of instruction fusion.

Definition at line 328 of file ARMSubtarget.h.

◆ hasMinSize()

bool llvm::ARMSubtarget::hasMinSize ( ) const

inline

Definition at line 374 of file ARMSubtarget.h.

References OptMinSize.

Referenced by llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), enableMachineScheduler(), and llvm::tryFoldSPUpdateIntoPushPop().

◆ hasVFP2Base()

bool llvm::ARMSubtarget::hasVFP2Base ( ) const

inline

Definition at line 304 of file ARMSubtarget.h.

Referenced by llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), isLegalAddressImmediate(), and isLegalT2AddressImmediate().

◆ hasVFP3Base()

bool llvm::ARMSubtarget::hasVFP3Base ( ) const

inline

Definition at line 305 of file ARMSubtarget.h.

◆ hasVFP4Base()

bool llvm::ARMSubtarget::hasVFP4Base ( ) const

inline

Definition at line 306 of file ARMSubtarget.h.

Referenced by useFPVFMx().

◆ ignoreCSRForAllocationOrder()

bool ARMSubtarget::ignoreCSRForAllocationOrder	(	const MachineFunction &	MF,
		MCRegister	PhysReg ) const

override

Definition at line 446 of file ARMSubtarget.cpp.

References llvm::MachineFunction::getFunction(), llvm::Function::hasMinSize(), and isThumb2().

◆ initializeSubtargetDependencies()

ARMSubtarget & ARMSubtarget::initializeSubtargetDependencies	(	StringRef	CPU,
		StringRef	FS )

initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.

Definition at line 73 of file ARMSubtarget.cpp.

References ARMSubtarget().

◆ isAClass()

bool llvm::ARMSubtarget::isAClass ( ) const

inline

Definition at line 379 of file ARMSubtarget.h.

References AClass, and ARMProcClass.

◆ isCortexA15()

bool llvm::ARMSubtarget::isCortexA15 ( ) const

inline

Definition at line 287 of file ARMSubtarget.h.

References ARMProcFamily.

Referenced by isLikeA9().

◆ isCortexA5()

bool llvm::ARMSubtarget::isCortexA5 ( ) const

inline

These functions are obsolete, please consider adding subtarget features or properties instead of calling them.

Definition at line 283 of file ARMSubtarget.h.

References ARMProcFamily.

◆ isCortexA7()

bool llvm::ARMSubtarget::isCortexA7 ( ) const

inline

Definition at line 284 of file ARMSubtarget.h.

References ARMProcFamily.

Referenced by adjustDefLatency().

◆ isCortexA8()

bool llvm::ARMSubtarget::isCortexA8 ( ) const

inline

Definition at line 285 of file ARMSubtarget.h.

References ARMProcFamily.

Referenced by adjustDefLatency().

◆ isCortexA9()

bool llvm::ARMSubtarget::isCortexA9 ( ) const

inline

Definition at line 286 of file ARMSubtarget.h.

References ARMProcFamily.

Referenced by isLikeA9().

◆ isCortexM3()

bool llvm::ARMSubtarget::isCortexM3 ( ) const

inline

Definition at line 289 of file ARMSubtarget.h.

References ARMProcFamily.

◆ isCortexM55()

bool llvm::ARMSubtarget::isCortexM55 ( ) const

inline

Definition at line 290 of file ARMSubtarget.h.

References ARMProcFamily.

◆ isCortexM7()

bool llvm::ARMSubtarget::isCortexM7 ( ) const

inline

Definition at line 291 of file ARMSubtarget.h.

References ARMProcFamily.

◆ isCortexM85()

bool llvm::ARMSubtarget::isCortexM85 ( ) const

inline

Definition at line 292 of file ARMSubtarget.h.

References ARMProcFamily.

◆ isCortexR5()

bool llvm::ARMSubtarget::isCortexR5 ( ) const

inline

Definition at line 294 of file ARMSubtarget.h.

References ARMProcFamily.

◆ isGVIndirectSymbol()

bool ARMSubtarget::isGVIndirectSymbol ( const GlobalValue * GV ) const

True if the GV will be accessed via an indirect symbol.

Definition at line 318 of file ARMSubtarget.cpp.

References llvm::GlobalValue::hasCommonLinkage(), llvm::GlobalValue::isDeclarationForLinker(), isTargetMachO(), and TM.

◆ isGVInGOT()

bool ARMSubtarget::isGVInGOT ( const GlobalValue * GV ) const

Returns the constant pool modifier needed to access the GV.

Definition at line 332 of file ARMSubtarget.cpp.

References llvm::GlobalValue::isDSOLocal(), isTargetELF(), and TM.

◆ isKrait()

bool llvm::ARMSubtarget::isKrait ( ) const

inline

Definition at line 295 of file ARMSubtarget.h.

References ARMProcFamily.

Referenced by isLikeA9().

◆ isLikeA9()

bool llvm::ARMSubtarget::isLikeA9 ( ) const

inline

Definition at line 293 of file ARMSubtarget.h.

References isCortexA15(), isCortexA9(), and isKrait().

Referenced by adjustDefLatency().

◆ isLittle()

bool llvm::ARMSubtarget::isLittle ( ) const

inline

Definition at line 407 of file ARMSubtarget.h.

References IsLittle.

Referenced by PerformMVEVMULLCombine(), and PerformVMOVRRDCombine().

◆ isMClass()

bool llvm::ARMSubtarget::isMClass ( ) const

inline

Definition at line 377 of file ARMSubtarget.h.

References ARMProcClass, and MClass.

Referenced by llvm::ARMFunctionInfo::ARMFunctionInfo(), enableMachineScheduler(), GetBranchTargetEnforcement(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), and LowerATOMIC_FENCE().

◆ isR9Reserved()

bool llvm::ARMSubtarget::isR9Reserved ( ) const

inline

Definition at line 381 of file ARMSubtarget.h.

References isTargetMachO().

Referenced by llvm::ARMBaseRegisterInfo::getRegPressureLimit(), and llvm::ARMBaseRegisterInfo::getReservedRegs().

◆ isRClass()

bool llvm::ARMSubtarget::isRClass ( ) const

inline

Definition at line 378 of file ARMSubtarget.h.

References ARMProcClass, and RClass.

◆ isReadTPSoft()

bool llvm::ARMSubtarget::isReadTPSoft ( ) const

inline

Definition at line 361 of file ARMSubtarget.h.

◆ isROPI()

bool ARMSubtarget::isROPI ( ) const

Definition at line 309 of file ARMSubtarget.cpp.

References llvm::Reloc::ROPI, llvm::Reloc::ROPI_RWPI, and TM.

Referenced by allowPositionIndependentMovt(), and promoteToConstantPool().

◆ isRWPI()

bool ARMSubtarget::isRWPI ( ) const

Definition at line 313 of file ARMSubtarget.cpp.

References llvm::Reloc::ROPI_RWPI, llvm::Reloc::RWPI, and TM.

◆ isSwift()

bool llvm::ARMSubtarget::isSwift ( ) const

inline

Definition at line 288 of file ARMSubtarget.h.

References ARMProcFamily, and llvm::CallingConv::Swift.

Referenced by adjustDefLatency().

◆ isTargetAEABI()

bool llvm::ARMSubtarget::isTargetAEABI ( ) const

inline

Definition at line 348 of file ARMSubtarget.h.

References TargetTriple.

Referenced by CC_ARM_AAPCS_Custom_Aggregate().

◆ isTargetAndroid()

bool llvm::ARMSubtarget::isTargetAndroid ( ) const

inline

Definition at line 365 of file ARMSubtarget.h.

References TargetTriple.

◆ isTargetCOFF()

bool llvm::ARMSubtarget::isTargetCOFF ( ) const

inline

Definition at line 344 of file ARMSubtarget.h.

References TargetTriple.

◆ isTargetDarwin()

bool llvm::ARMSubtarget::isTargetDarwin ( ) const

inline

These properties are per-module, please use the TargetMachine TargetTriple.

Definition at line 335 of file ARMSubtarget.h.

References TargetTriple.

Referenced by llvm::ARMAsmPrinter::emitInstruction(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), getFramePointerReg(), llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask(), llvm::ARMBaseRegisterInfo::getTLSCallPreservedMask(), and useFPVFMx().

◆ isTargetDriverKit()

bool llvm::ARMSubtarget::isTargetDriverKit ( ) const

inline

Definition at line 339 of file ARMSubtarget.h.

References TargetTriple.

◆ isTargetEHABICompatible()

bool llvm::ARMSubtarget::isTargetEHABICompatible ( ) const

inline

Definition at line 356 of file ARMSubtarget.h.

References TargetTriple.

◆ isTargetELF()

bool llvm::ARMSubtarget::isTargetELF ( ) const

inline

Definition at line 345 of file ARMSubtarget.h.

References TargetTriple.

Referenced by allowPositionIndependentMovt(), and isGVInGOT().

◆ isTargetGNUAEABI()

bool llvm::ARMSubtarget::isTargetGNUAEABI ( ) const

inline

Definition at line 350 of file ARMSubtarget.h.

References TargetTriple.

◆ isTargetIOS()

bool llvm::ARMSubtarget::isTargetIOS ( ) const

inline

Definition at line 336 of file ARMSubtarget.h.

References TargetTriple.

◆ isTargetLinux()

bool llvm::ARMSubtarget::isTargetLinux ( ) const

inline

Definition at line 340 of file ARMSubtarget.h.

References TargetTriple.

Referenced by useFastISel().

◆ isTargetMachO()

bool llvm::ARMSubtarget::isTargetMachO ( ) const

inline

Definition at line 346 of file ARMSubtarget.h.

References TargetTriple.

Referenced by isGVIndirectSymbol(), isR9Reserved(), and useFastISel().

◆ isTargetMuslAEABI()

bool llvm::ARMSubtarget::isTargetMuslAEABI ( ) const

inline

Definition at line 352 of file ARMSubtarget.h.

References TargetTriple.

◆ isTargetNetBSD()

bool llvm::ARMSubtarget::isTargetNetBSD ( ) const

inline

Definition at line 341 of file ARMSubtarget.h.

References TargetTriple.

◆ isTargetWatchABI()

bool llvm::ARMSubtarget::isTargetWatchABI ( ) const

inline

Definition at line 338 of file ARMSubtarget.h.

References TargetTriple.

Referenced by useStride4VFPs().

◆ isTargetWatchOS()

bool llvm::ARMSubtarget::isTargetWatchOS ( ) const

inline

Definition at line 337 of file ARMSubtarget.h.

References TargetTriple.

◆ isTargetWindows()

bool llvm::ARMSubtarget::isTargetWindows ( ) const

inline

Definition at line 342 of file ARMSubtarget.h.

References TargetTriple.

Referenced by llvm::ARMAsmPrinter::emitInstruction(), getDivRemArgList(), getFramePointerReg(), isXRaySupported(), and useMovt().

◆ isThumb1Only()

bool llvm::ARMSubtarget::isThumb1Only ( ) const

inline

Definition at line 375 of file ARMSubtarget.h.

References isThumb().

Referenced by ARMSubtarget(), attachMEMCPYScratchRegs(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::emitLoadConstPool(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), enablePostRAMachineScheduler(), enablePostRAScheduler(), getGPRAllocationOrder(), getPushPopSplitVariation(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), isLegalAddressImmediate(), LowerADDSUBSAT(), llvm::ARMCallLowering::lowerCall(), LowerPREFETCH(), LowerSTORE(), PerformAddcSubcCombine(), PerformADDECombine(), PerformAddeSubeCombine(), PerformANDCombine(), PerformMULCombine(), PerformORCombine(), PerformORCombineToBFI(), PerformXORCombine(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), useFastISel(), and llvm::ThumbRegisterInfo::useFPForScavengingIndex().

◆ isThumb2()

bool llvm::ARMSubtarget::isThumb2 ( ) const

inline

Definition at line 376 of file ARMSubtarget.h.

References isThumb().

Referenced by getGPRAllocationOrder(), ignoreCSRForAllocationOrder(), isLegalAddressImmediate(), LowerPREFETCH(), and PerformMinMaxToSatCombine().

◆ isXRaySupported()

bool ARMSubtarget::isXRaySupported ( ) const

override

Definition at line 134 of file ARMSubtarget.cpp.

References hasARMOps(), and isTargetWindows().

◆ ParseSubtargetFeatures()

void llvm::ARMSubtarget::ParseSubtargetFeatures	(	StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS )

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Definition of function is auto generated by tblgen.

References ARMSubtarget().

◆ restrictIT()

bool llvm::ARMSubtarget::restrictIT ( ) const

inline

Definition at line 403 of file ARMSubtarget.h.

References RestrictIT.

◆ supportsTailCall()

bool llvm::ARMSubtarget::supportsTailCall ( ) const

inline

Definition at line 399 of file ARMSubtarget.h.

References SupportsTailCall.

◆ useAA()

bool llvm::ARMSubtarget::useAA ( ) const

inlineoverride

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 429 of file ARMSubtarget.h.

◆ useDFAforSMS()

bool ARMSubtarget::useDFAforSMS ( ) const

override

Definition at line 365 of file ARMSubtarget.cpp.

◆ useFastISel()

bool ARMSubtarget::useFastISel ( ) const

True if fast-isel is used.

Definition at line 401 of file ARMSubtarget.cpp.

References ForceFastISel, isTargetLinux(), isTargetMachO(), isThumb(), isThumb1Only(), and TM.

Referenced by llvm::ARM::createFastISel().

◆ useFPVFMx()

bool llvm::ARMSubtarget::useFPVFMx ( ) const

inline

Definition at line 315 of file ARMSubtarget.h.

References hasVFP4Base(), and isTargetDarwin().

Referenced by useFPVFMx16(), and useFPVFMx64().

◆ useFPVFMx16()

bool llvm::ARMSubtarget::useFPVFMx16 ( ) const

inline

Definition at line 318 of file ARMSubtarget.h.

References useFPVFMx().

◆ useFPVFMx64()

bool llvm::ARMSubtarget::useFPVFMx64 ( ) const

inline

Definition at line 319 of file ARMSubtarget.h.

References useFPVFMx().

◆ useFPVMLx()

bool llvm::ARMSubtarget::useFPVMLx ( ) const

inline

Definition at line 314 of file ARMSubtarget.h.

◆ useMachinePipeliner()

bool llvm::ARMSubtarget::useMachinePipeliner ( ) const

inline

Definition at line 373 of file ARMSubtarget.h.

Referenced by enableMachinePipeliner().

◆ useMachineScheduler()

bool llvm::ARMSubtarget::useMachineScheduler ( ) const

inline

Definition at line 372 of file ARMSubtarget.h.

Referenced by enableMachineScheduler().

◆ useMovt()

bool ARMSubtarget::useMovt ( ) const

Definition at line 393 of file ARMSubtarget.cpp.

References isTargetWindows(), and OptMinSize.

Referenced by llvm::ConstantMaterializationCost().

◆ useMulOps()

bool llvm::ARMSubtarget::useMulOps ( ) const

inline

Definition at line 313 of file ARMSubtarget.h.

References UseMulOps.

Referenced by AddCombineTo64bitMLAL().

◆ useNEONForSinglePrecisionFP()

bool llvm::ARMSubtarget::useNEONForSinglePrecisionFP ( ) const

inline

Definition at line 300 of file ARMSubtarget.h.

◆ useStride4VFPs()

bool ARMSubtarget::useStride4VFPs ( ) const

Definition at line 385 of file ARMSubtarget.cpp.

References isTargetWatchABI(), and OptMinSize.

Member Data Documentation

◆ ARMArch

ARMArchEnum llvm::ARMSubtarget::ARMArch = ARMv4t

protected

ARMArch - ARM architecture.

Definition at line 139 of file ARMSubtarget.h.

◆ ARMProcClass

ARMProcClassEnum llvm::ARMSubtarget::ARMProcClass = None

protected

ARMProcClass - ARM processor class: None, AClass, RClass or MClass.

Definition at line 136 of file ARMSubtarget.h.

Referenced by isAClass(), isMClass(), and isRClass().

◆ ARMProcFamily

ARMProcFamilyEnum llvm::ARMSubtarget::ARMProcFamily = Others

protected

ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.

Definition at line 133 of file ARMSubtarget.h.

Referenced by isCortexA15(), isCortexA5(), isCortexA7(), isCortexA8(), isCortexA9(), isCortexM3(), isCortexM55(), isCortexM7(), isCortexM85(), isCortexR5(), isKrait(), and isSwift().

◆ CPUString

std::string llvm::ARMSubtarget::CPUString

protected

CPUString - String name of used CPU.

Definition at line 159 of file ARMSubtarget.h.

Referenced by ARMSubtarget(), and getCPUString().

◆ InstrItins

InstrItineraryData llvm::ARMSubtarget::InstrItins

protected

Selected instruction itineraries (one entry per itinerary class.)

Definition at line 196 of file ARMSubtarget.h.

Referenced by getInstrItineraryData().

◆ IsLittle

bool llvm::ARMSubtarget::IsLittle

protected

IsLittle - The target is Little Endian.

Definition at line 187 of file ARMSubtarget.h.

Referenced by ARMSubtarget(), and isLittle().

◆ LdStMultipleTiming

ARMLdStMultipleTiming llvm::ARMSubtarget::LdStMultipleTiming = SingleIssue

protected

What kind of timing do load multiple/store multiple have (double issue, single issue etc).

Definition at line 168 of file ARMSubtarget.h.

Referenced by getLdStMultipleTiming().

◆ MaxInterleaveFactor

unsigned llvm::ARMSubtarget::MaxInterleaveFactor = 1

protected

Definition at line 161 of file ARMSubtarget.h.

Referenced by getMaxInterleaveFactor().

◆ MVEVectorCostFactor

unsigned llvm::ARMSubtarget::MVEVectorCostFactor = 0

protected

The cost factor for MVE instructions, representing the multiple beats an.

Definition at line 180 of file ARMSubtarget.h.

Referenced by getMVEVectorCostFactor().

◆ Options

const TargetOptions& llvm::ARMSubtarget::Options

protected

Options passed via command line that could influence the target.

Definition at line 199 of file ARMSubtarget.h.

Referenced by ARMSubtarget().

◆ OptMinSize

bool llvm::ARMSubtarget::OptMinSize = false

protected

OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.

Definition at line 184 of file ARMSubtarget.h.

Referenced by ARMSubtarget(), hasMinSize(), useMovt(), and useStride4VFPs().

◆ PartialUpdateClearance

unsigned llvm::ARMSubtarget::PartialUpdateClearance = 0

protected

Clearance before partial register updates (in number of instructions)

Definition at line 164 of file ARMSubtarget.h.

Referenced by getPartialUpdateClearance().

◆ PreferBranchLogAlignment

unsigned llvm::ARMSubtarget::PreferBranchLogAlignment = 0

protected

What alignment is preferred for loop bodies and functions, in log2(bytes).

Definition at line 175 of file ARMSubtarget.h.

Referenced by getPreferBranchLogAlignment().

◆ PreISelOperandLatencyAdjustment

int llvm::ARMSubtarget::PreISelOperandLatencyAdjustment = 2

protected

The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands.

Definition at line 172 of file ARMSubtarget.h.

Referenced by getPreISelOperandLatencyAdjustment().

◆ RestrictIT

bool llvm::ARMSubtarget::RestrictIT = false

protected

RestrictIT - If true, the subtarget disallows generation of complex IT blocks.

Definition at line 152 of file ARMSubtarget.h.

Referenced by restrictIT().

◆ SchedModel

MCSchedModel llvm::ARMSubtarget::SchedModel

protected

SchedModel - Processor specific instruction costs.

Definition at line 193 of file ARMSubtarget.h.

Referenced by getMispredictionPenalty().

◆ stackAlignment

Align llvm::ARMSubtarget::stackAlignment = Align(4)

protected

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.

Definition at line 156 of file ARMSubtarget.h.

Referenced by getStackAlignment().

◆ SupportsTailCall

bool llvm::ARMSubtarget::SupportsTailCall = false

protected

SupportsTailCall - True if the OS supports tail call.

The dynamic linker must be able to synthesize call stubs for interworking between ARM and Thumb.

Definition at line 148 of file ARMSubtarget.h.

Referenced by supportsTailCall().

◆ TargetTriple

Triple llvm::ARMSubtarget::TargetTriple

protected

TargetTriple - What processor and OS we're targeting.

Definition at line 190 of file ARMSubtarget.h.

Referenced by ARMSubtarget(), getTargetTriple(), isTargetAEABI(), isTargetAndroid(), isTargetCOFF(), isTargetDarwin(), isTargetDriverKit(), isTargetEHABICompatible(), isTargetELF(), isTargetGNUAEABI(), isTargetIOS(), isTargetLinux(), isTargetMachO(), isTargetMuslAEABI(), isTargetNetBSD(), isTargetWatchABI(), isTargetWatchOS(), and isTargetWindows().

◆ TM

const ARMBaseTargetMachine& llvm::ARMSubtarget::TM

protected

Definition at line 201 of file ARMSubtarget.h.

Referenced by ARMSubtarget(), isGVIndirectSymbol(), isGVInGOT(), isROPI(), isRWPI(), and useFastISel().

◆ UseMulOps

bool llvm::ARMSubtarget::UseMulOps = false

protected

UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.

Definition at line 143 of file ARMSubtarget.h.

Referenced by ARMSubtarget(), and useMulOps().

The documentation for this class was generated from the following files:

lib/Target/ARM/ARMSubtarget.h
lib/Target/ARM/ARMSubtarget.cpp

Public Types

Public Member Functions

Protected Types

Protected Attributes

Detailed Description

Member Enumeration Documentation

◆ ARMArchEnum

◆ ARMLdStMultipleTiming

◆ ARMProcClassEnum

◆ ARMProcFamilyEnum

◆ PushPopSplitVariation

Constructor & Destructor Documentation

◆ ARMSubtarget()

Member Function Documentation

◆ allowPositionIndependentMovt()

◆ allowsUnalignedMem()

◆ enableMachinePipeliner()

◆ enableMachineScheduler()

◆ enablePostRAMachineScheduler()

◆ enablePostRAScheduler()

◆ enableSubRegLiveness()

◆ getCallLowering()

◆ getCPUString()

◆ getDualLoadStoreAlignment()

◆ getFrameLowering()

◆ getFramePointerReg()

◆ getGPRAllocationOrder()

◆ getInstrInfo()

◆ getInstrItineraryData()

◆ getInstructionSelector()

◆ getLdStMultipleTiming()

◆ getLegalizerInfo()

◆ getMaxInlineSizeThreshold()

◆ getMaxInterleaveFactor()

◆ getMaxMemcpyTPInlineSizeThreshold()

◆ getMispredictionPenalty()

◆ getMVEVectorCostFactor()

◆ getPartialUpdateClearance()

◆ getPreferBranchLogAlignment()

◆ getPreISelOperandLatencyAdjustment()

◆ getPushPopSplitVariation()

◆ getRegBankInfo()

◆ getRegisterInfo()

◆ getReturnOpcode()

◆ getSelectionDAGInfo()

◆ getStackAlignment()

◆ getTargetLowering()

◆ getTargetTriple()

◆ hasAnyDataBarrier()

◆ hasARMOps()

◆ hasBaseDSP()

◆ hasFPARMv8Base()

◆ hasFusion()

◆ hasMinSize()

◆ hasVFP2Base()

◆ hasVFP3Base()

◆ hasVFP4Base()

◆ ignoreCSRForAllocationOrder()

◆ initializeSubtargetDependencies()

◆ isAClass()

◆ isCortexA15()

◆ isCortexA5()

◆ isCortexA7()

◆ isCortexA8()

◆ isCortexA9()

◆ isCortexM3()

◆ isCortexM55()

◆ isCortexM7()

◆ isCortexM85()

◆ isCortexR5()

◆ isGVIndirectSymbol()

◆ isGVInGOT()

◆ isKrait()

◆ isLikeA9()

◆ isLittle()

◆ isMClass()

◆ isR9Reserved()

◆ isRClass()

◆ isReadTPSoft()

◆ isROPI()