Hindawi Publishing Corporation

VLSI Design
Volume 2012, Article ID 173079, 18 pages
doi:10.1155/2012/173079

Research Article
Performance Analysis of High Speed Hybrid CMOS Full Adder
Circuits for Low Voltage VLSI Design

Subodh Wairya,1 Rajendra Kumar Nagaria,2 and Sudarshan Tiwari2

1 Department of Electronics Engineering, Institute of Engineering & Technology (IET), Lucknow 226021, India
2 Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology (MNNIT),
Allahabad 211004, India

Correspondence should be addressed to Subodh Wairya, [email protected]

Received 28 June 2011; Revised 2 November 2011; Accepted 24 November 2011

Academic Editor: Jose Carlos Monteiro

Copyright © 2012 Subodh Wairya et al. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly
cited.

This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design
full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed.
This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one
unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use
MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of
digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder
circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and
energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits
against the reported conventional adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso
Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

1. Introduction higher speed, longer battery life, and enhanced reliability.

The XOR-XNOR circuits are basic building blocks in various
It is time we explore the well-engineered deep submicron circuits especially arithmetic circuits (adders & multipliers),
CMOS technologies to address the challenging criteria of compressors, comparators, parity checkers, code converters,
these emerging low-power and high-speed communication error-detecting or error-correcting codes and phase detector.
digital signal processing chips. The performance of many Adder is the core element of complex arithmetic circuits
applications as digital signal processing depends upon the like addition, multiplication, division, exponentiation, and
performance of the arithmetic circuits to execute complex so forth. There are standard implementations with various
algorithms such as convolution, correlation, and digital fil- logic styles that have been used in the past to design full-
tering. Fast arithmetic computation cells including adders adder cells [1–4] and the same are used for comparison
and multipliers are the most frequently and widely used in this paper. Although they all have similar function, the
circuits in very-large-scale integration (VLSI) systems. The way of producing the intermediate nodes and the transistor
semiconductor industry has witnessed an explosive growth count is varied. Different logic styles tend to favor one
of integration of sophisticated multimedia-based applica- performance aspect at the expense of the others. The logic
tions into mobile electronics gadgetry since the last decade. style used in logic gates basically influences the speed, size,
However, the critical concern in this arena is to reduce the power dissipation, and the wiring complexity of a circuit.
increase in power consumption beyond a certain range of The circuit delay is determined by the number of inversion
operating frequency. Moreover, with the explosive growth, levels, the number of transistors in series, transistor sizes
the demand, and the popularity of portable electronic prod- (i.e., channel widths), and the intracell wiring capacitances.
ucts, the designers are driven to strive for smaller silicon area, Circuit size depends upon the number of transistors, their
2 VLSI Design

sizes and on the wiring complexity. Some of them use one VDD
logic style for the whole full adder while the other use more
than one logic style for their implementation.
Power is one of the vital resources, hence the designers A B B A B C C
try to save it while designing a system. Power dissipation de-
pends upon the switching activity, node capacitances (made B
up of gate, diffusion, and wire capacitances), and control cir-
cuit size. At the device level, reducing the supply voltage VDD C A
and reducing the threshold voltage accordingly would reduce A
the power consumption. Scaling the supply voltage appears
to be the well-known means to reduce power consumption.
However, lower-supply voltage increases circuit delay and Carry Sum A
degrades the drivability of the cells designed with a certain C A
logic style. One of the most significant obstacle in decreasing B
the supply voltage is the large transistor count and Vth loss
problem. By selecting proper (W/L) ratio we can minimize
the power dissipation without decreasing the supply voltage. A B B A B C C
To summarize, some of the performance criteria are con-
sidered in the design and evaluation of adder cells and some
are utilized for the ease of design, robustness, silicon area,
delay, and power consumption. The paper is organized sec-
tion wise. Section 2 describes the review of full adder circuit Figure 1: C-CMOS adder cell.
topologies. Section 3 illustrates the concept of SUM func-
tion-based hybrid full adders topologies and highlights some
1-bit adder cells, which is based on XOR-XNOR (3T) cir- Full adder circuits can be divided into two groups on
cuits. A review of Majority function, MOS capacitor charac- the basis of output. The first group of full adders have full
teristics, and three-input and five-input Majority function swing output. C-CMOS, CPL, TGA, TFA, Hybrid, 14T, and
(MOSCAPs) based full adder topologies has been discussed 16T belong to the first group [5–20, 29–31]. The second
in Section 4. In Section 5, implementations of Hybrid XOR- group comprises of full adders (10T, 9T and 8T) without
XNOR (3T) and Majority-function-based full adder meth- full swing outputs [21–28]. These full adders usually have
odologies are discussed. The simulation results are analyzed low number of transistors- (3T-) based XOR-XNOR circuit,
and compared in Section 6. Finally, Section 7 concludes the less power consumption, and less area occupation. The
paper. nonfull swing full adders are useful in building up larger
circuits as multiple bit input adder and multipliers. One
such application is the Manchester Carry-Look Ahead chain.
2. Review of Full Adder Topologies The full adders of first group have good driving ability, high
number of transistors, large area, and usually higher power
In recent years, several variants of different logic styles have consumption in comparison to the second group.
been proposed to implement 1-bit adder cells [5–28]. There There are standard implementations for the full-adder
are two types of full adders in case of logic structure. One cells which are used as the basis of comparison in this paper.
is static and the other is dynamic style. Static full adders Some of the standard implementations are as follows.
are commonly more reliable, simpler and are lower power CMOS logic styles have been used to implement the low-
consuming than dynamic ones. Dynamic is an alternative power 1-bit adder cells. In general, they can be broadly di-
logic style to design a logic function. It has some advantages vided into two major categories: the Complementary CMOS
over the static mode such as faster switching speeds, no static and the Pass-Transistor logic circuits. The complementary
power consumption, nonratioed logic, full swing voltage CMOS (C-CMOS) full adder (Figure 1) is based on the
levels, and lesser number of transistors. An N input logic regular CMOS structure [3, 4, 29]. The advantage of com-
function requires N+2 transistors versus 2N transistors in plementary CMOS style is its robustness against voltage scal-
the standard CMOS logic. The area advantage comes from ing and transistor sizing, which are essential to provide relia-
the fact that the pMOS network of a dynamic CMOS gate ble operation at low voltage with arbitrary transistor sizes.
consists of only one transistor. This also results in a reduction The pass-transistor logic (PTL) is a better way to imple-
in the capacitive load at the output node, which is the basis ment circuits designed for low power applications. The low
for the delay advantage. There are various issues related power pass-transistor logic and its design analysis procedures
to the full adder like power consumption, performance, were reported in [12, 13]. Its advantage is that one pass-
area, noise immunity, regularity and good driving ability. transistor network (either pMOS or nMOS) is sufficient to
Many researchers have combined these two structures and implement the logic function, which results in lower number
have proposed hybrid dynamic-static full adders. They of transistors and smaller input load. Moreover, direct VDD -
have investigated different approaches realizing adders using to-ground paths, which may lead to short-circuit energy
CMOS technology each having its own pros and cons. dissipation, are eliminated.
VLSI Design 3

VDD VDD
B C
C TG

Carry Sum
B
Sum C A
A C TG

B TG

A
B C
A
B
Figure 2: TG-Pseudo adder cell. B TG

Carry

Pseudo nMOS full adder cell operates on pseudo logic, TG

which is referred to as ratioed style. This full adder cell uses C TG
14 transistors to realize the negative addition function. The
advantage of pseudo nMOS adder cell is its higher speed B
(compared to conventional full adder) and less transistor
count. The disadvantage of pseudo nMOS cell is the static Figure 3: TG adder cell.
power consumption of the pull-up transistor as well as the
reduced output voltage swing, which makes this adder cell
more susceptible to noise. To increase the output swing, into various categories depending upon their structure and
CMOS inverter is added to this circuit. logical expression of the Sum and Carry output signals. All
Newly designed full adder [20] is a combination of low hybrid designs use the best available modules implemented
power transmission gates and pseudo nMOS gates as depict- using different logic styles or enhance the available modules
ed in Figure 2. Transmission gate consists of a pMOS transis- in an attempt to build a low power consuming full-adder
tor and an nMOS transistor that are connected in parallel, cell [17–19]. Most full adder topologies are based on two
which is a particular type of pass-transistor logic circuit. XOR circuits: one to generate H (XOR) with H (XNOR),
There is no voltage drop at output node, but it requires twice and the other to generate the Sum output. The carry signal is
the number of transistors to design similar function. obtained by using one MUX (multiplexer):
Another full adder is the Complementary Pass Transistor
Logic (CPL) with swing restoration, which uses 32 transistors Sum = A ⊕ B ⊕ C, Carry = AB + C(A ⊕ B),
[5, 6, 30, 31]. CPL adder produces many intermediate nodes
H = A ⊕ B, Sum = H ⊕ C, (1)
and their complement to give the outputs. The most impor-
tant features of CPL include the small stack height and low Carry = A · H + C · H.
output voltage swing at the internal node which contribute
to reduction in power consumption. The CPL suffers from
static power consumption due to the low swing at the gates 3.1. XOR-XNOR Topologies. In [28, 32–35], the XOR-XNOR
of the output inverters. Double pass-transistor logic (DPL) circuit designed with static CMOS logic with complementary
[8] and swing restored pass-transistor logic (SRPL) [9, 10] are pull-up pMOS and pull-down nMOS networks is the
related to CPL. conventional one, but it requires more number of CMOS
Some designs of the full adder circuit based on trans- transistors. This circuit may operate with full output voltage
mission gates are shown in Figure 3. Transmission gate logic swing. Different XOR/XNOR topologies are illustrated in
circuit is a special kind of pass-transistor logic circuit [4, 5, Figure 4. A PTL based 6-transitor XOR-XNOR circuit
25]. The main disadvantage of transmission gate logic is that presented in [34] has full output voltage swing and better
it requires twice the number of transistors than pass-transis- driving capability.
tor logic or more to implement the same circuit. TG gate full A new set of low power four transistor (4T) XOR and
adder cell has 20 transistors. Similarly, transmission function XNOR circuits called powerless P-XOR and Groundless G-
full adder (TFA) cell has 16 transistors [4, 29]. It exhibits XNOR, respectively, is proposed in [25–28, 32]. The P-XOR
better speed and less power dissipation than the conventional and G-XNOR circuits consume less power than other designs
CMOS adder due to the small transistor stack height. because they have no direct supply voltage (VDD ) or ground
connection. The performance of the complex logic circuits
is affected by the individual performance of the XOR-XNOR
3. Sum Function-Based Hybrid circuits that are included in them. An XOR and XNOR func-
Full Adder Topologies tion with low circuit complexity can be achieved with only
three transistors (3T) in PTL. Despite the saving in transistor
More than one logic style is used for implementation of the count, the output voltage level is degraded at certain input
hybrid full adders. The hybrid adder cells may be classified signal combinations.
4 VLSI Design

VDD
VDD
A XOR B

A B A B A XOR B

A XNOR B

(a) XOR-XNOR (6T) (b) 4T XOR (4T)

B A VDD
A B B
A XOR B
A
A
A VDD
A XOR B VDD
B A XNOR B
B A

B
(c) XOR (3T) (d) XOR-XNOR (3T)

Figure 4: Basic designs of XOR-XNOR gate found in literature.

A XOR A XOR XOR Sum

logic MUX Sum logic logic
B B
Sel

C A
A XNOR MUX Carry
B logic A C
MUX Sel
Carry
Sel

Figure 6: Centralized XOR-XNOR based-adder.

C

Figure 5: Cascaded XOR-XNOR based-adder.

3.3. Centralized Output Based Adders (Group 2). In this
category, Sum and Carry are generated using intermediate
Generally, the main aim is to reduce the number of tran- signals XOR and XNOR. In this group, output Sum and
sistors in the adder cell and consequently to reduce the num- Carry are generated faster than the outputs in cascaded
ber of power dissipating nodes. This is achieved by utilizing output full adders. The key point here is to produce inter-
intrinsically low power consuming logic styles like TFA, mediate signals simultaneously. Otherwise, there may be
TGA or simply passing transistors. There are three main glitches, unnecessary power consumption, and longer delay.
components to design a hybrid full adder circuit [19]. These Figure 6 shows the basic blocks of this category. TGA and
are XOR or XNOR, Carry generator and Sum generator. TFA are in this category. Some of the hybrid full adders do
Hybrid adders may be classified into two groups which are not belong to any of these two groups, such as Complementa-
as follows. ry and Level Restoring Carry Logic (CLRCL) full adder [26]
and Multiplexer based (MBF 12T) full adder [18].
3.2. Cascaded Output Based Adders (Group 1). In this catego-
ry, signal Sum is generated using, either two cascaded XOR 3.4. 10T Full Adder. In [24] different components have been
or two cascaded XNOR modules. Figure 5 shows the basic combined to make 41 new 10T full adder full adders. Some
blocks of this category. Almost all the circuits in this category 10T full adders can be designed by interchanging the inputs
suffer from high delay in generating Sum and Carry signals. of the module having lowest propagation delay amongst all
The Static Energy Recovery full adder (SERF) falls under this the 10T full adder circuits. The design of the 10T adder
category [23]. cell is based on an optimized design for the XOR function
VLSI Design 5

A B C

C
Sum M6
A Sum
A B B
A B
Carry
A M7
M2 M3 M4
A
Carry VDD
A

B M1 M5 M8
Figure 7: XOR-XNOR- (3T-) based 10T full adder.
C

and pass transistor logic to implement the addition logic M9

function. Two XOR operations are required to calculate the
Sum function. Each XOR operation requires four transistors
(4T). 2X1 MUX is used for Carry function implemented Figure 8: 9T full adder.
using two transistors.
Another 10T full adder based on centralized structure
is shown in Figure 7. Intermediate XOR and XNOR are B A C
generated using three transistor (3T) XOR and XNOR gate.
Sum and Carry are generated using two double transistors M2 M3 M5 M6 M7
multiplexers. 3T XOR and XNOR consume high energy due C
Carry
to short circuit current in ratio logic. They all have double A B
threshold losses in full adder output terminals. This problem Sum M8
M1
usually prevents the full adder design from operating at low M4
supply voltage or cascading directly without extra buffering. A
The lowest possible power supply is limited to 2Vtn + Vtp
where Vtn and Vtp are the threshold voltages of nMOS and Figure 9: 8T full adder.
pMOS respectively. The basic advantages of 10T transistor
full adders are: less area compared to higher gate count
full adders, lower power consumption and lower operating tox is the thickness of the oxide layer,
voltage. It becomes very difficult and even obsolete to keep
full voltage swing operation as the designs with fewer transis- αl , αv , and αw are the process dependent parameters.
tor count and lower power consumption are pursued. The above equation shows that by increasing channel width
(W) it is possible to decrease the threshold voltage (Vth ).
3.5. 9T Full Adder. In nine transistor (9T) full adder circuit, So it is possible to minimize the voltage degradation due to
we have only one 3T XOR gate as is shown in the Figure 8 threshold voltage by increasing the width of M3 transistor
[36]. The design of 3T (M1–M3) XOR circuit is based on a & keeping the length constant. In 9T full adder circuit pass
modified version of a CMOS inverter and a pMOS pass tran- transistor M4, M5 and M6, M7 are used for Carry and Sum
sistor. When A = 1 and B = 0, voltage degradation due to function respectively.
threshold drop occurs across transistor M3 and consequently
the output (M3) is degraded with respect to the input. The 3.6. 8T Full Adder. The design of an eight transistor (8T) full
voltage degradation due to threshold drop can be minimized adder using 3T XOR gates is shown in Figure 9 [37]. The
by increasing the W/L ratio of transistor M3. An equation Boolean equations for the design of the eight transistor full
relating threshold voltage of a MOS transistor to the channel adder are as follows:
length and width is given as
Sum = A ⊕ B ⊕ C,
   tox   (3)
VT = VT0 + γ VSB + φ0 − φ0 − αl VSB + φ0 Carry = BC + CA + AB = C(A ⊕ B) + AB.
L
(2)
tox tox   The Sum output function is obtained by a cascade of 3T
− αv (VDS ) + αW VSB + φ0 , XOR gates. Carry can be realized using a wired OR logic in
L L
accordance with the above equation.
where Another 8T full adder using centralizer output condi-
VT0 is the zero bias threshold voltage, tion contains three modules—two 3T XOR gates and one
multiplexer (2T). It can work at high speed with low power
γ is bulk threshold coefficient, dissipation due to minimum number of transistors and small
φ0 is 2φF , where φF is the Fermi potential, transistor delay.
6 VLSI Design

VDD
i1
V1 C1

Cap MP1
i2 V Majority. A
V2 C1 Buffer
Cap
NAND/NOR/Majority Not
B
i3 cX Cap
V3 C1
C
MN1

Figure 10: Implementation of Majority functions (MOSCAP).

4. Carry (Majority) Function-Based Hybrid Figure 11: Majority function- (MOSCAP-) based logic gates.
Full Adder Topologies
The Majority function is a logic circuit that functions as a
inverter. When the majority of inputs are “0”, the output
majority vote to determine the output of the circuits [38].
of capacitor network is considered as logic “0” by the
This function has only odd number of inputs. Its output is
CMOS buffer and consequently the output of buffer is 0 V.
equal to “1” when the number of input logic “1” is more
When the majority of inputs are logic “1”, the output of
than logic “0”. Comparing to the XOR implementations of
capacitor network is considered logic “1” by the CMOS
full adder cells, Majority-based full adders are more reliable
buffer and consequently the output of buffer is VDD . The
and robust [38]. Moreover, the bridge style full adder circuits
input capacitance of the CMOS buffer is negligible and
[39] by sharing transistors can operate faster and are smaller
has no effect on operation of the circuit. Three capacitors
than the conventional CMOS full adder circuits.
perform voltage summation to implement scaled-linear sum.
Through superposition of input capacitors, increased input
4.1. Literature Review of Majority Functions. Boolean algebra voltage is scaled at point V as shown in Figure 10 and given
with three variables is used to facilitate the conversion of in Table 2 [40].
a sum-of-products expression to minimize majority logic
as shown in Table 1 [38]. Three binary variables can only
4.3. MOS Capacitor (MOSCAP) Structure. In this section
produce eight unique minterms. Any three-variable Boolean
hardware implementation and construction of MOSCAP are
function can be represented by the combinations of up to
discussed. Tying the drain and source of a MOSFET together
eight of these minterms. The three-variable Boolean function
results in a MOSCAP. Many realizable alternatives such as
of 5–7 minterms can be represented using the complement
Poly-Insulator-Poly capacitors (PIPCAP), Metal-Insulator-
form of 3–1 minterms. Based on DeMorgan’s theorem, a
Metal capacitors (MIMCAP), or Metal-Oxide-Semicon-
Boolean function, expressed as the sum of several minterms,
ductor capacitors (MOSCAP) can be utilized for realizing the
can also be expressed as the complement of the sum of the
capacitor network. However, MOSCAP has an advantage of
remaining minterms. The simplified majority expressions for
more capacitance; less chip area. The nMOSCAP usually has
13 standard functions are given in Table 1.
lesser capacitance in comparison to pMOSCAP for the same
area, so pMOSCAP is used for implementing the capacitor
4.2. Circuit-Interpretation-of-MOS Capacitor- (MOSCAP-) network. Table 3 shows that the variation of MOS capacitor
Based Majority Not Function. The majority structure is im- with respect to channel width of MOS transistor.
plemented by three input capacitors. These three input ca-
pacitors prepare an input voltage that is applied for driving
4.4. Implementation of (NAND, NOR and Majority Not)
static CMOS buffer. The majority gates may be designed with
Gates Using MOSCAP Majority Function. Figure 11 shows
more inputs by this method by increasing the number of
the circuit used to implement Majority Not function with
input capacitors. The capacitor network is used to provide
inverter utilizing high-Vth for both nMOS and pMOS. This
voltage division for implementing majority logic as explained
circuit can be used to implement NAND gate using high-
below.
Vth nMOS and low-Vth pMOS, and NOR gate using low-
Total current I at node V = I1 + I2 + I3 ,
Vth nMOS and high-Vth pMOS. The Majority gates may be
(V )cx s = (V1 − V )c1 s + (V2 − V )c1 s + (V3 − V )c1 s designed with more inputs by this method by increasing the
number of input capacitors. The capacitor network is used to
= (cX + 3c1 )V = (V1 + V2 + V3 )c1 , provide voltage division for implementing majority logic.
(4)
  There are two methods to design the NAND and NOR
c1
V = (V1 + V2 + V3 ) . logic circuits. First method is the transistor sizing that shifts
3c1 + cX
the voltage transfer curve (VTC) to the left and right by
The input capacitors shown in Figure 10 are used to changing the ratio of (W/L)n to (W/L)p. Raising this ratio
prepare an input voltage that is applied for driving static moves VTC to the left; therefore, this circuit will operate as
VLSI Design 7

Table 1: Majority expression of standard logic functions.

Standard Boolean function Majority expression Function implementation diagram
A
1 M F
F=A M(A, 0, 1) 0

A
0 M F
F =A·B M(A, B, 0)
B

A
0 M F
B 0 M
F =A·B·C M(M(A, B, 0), C, 0)
C

A
0 M
B

0 M
C
F
F =A·B·C+A·B·C M {M(M(A, 0, B), C, 0), M(M(A, B, 0), C, 0), 1} 1 M
C
0 M
A
0 M
B

A
0 M F
B 1 M

C
F =A·B+A·B·C M {M(A, 0, B), M(M(A, B, 0), C, 0), 1} 0 M

A
0 M
B

A
0 M
B
F
1 M
F =A·B+B·C M {M(A, 0, B), M(B, 0, C), 1}
B
0 M
C

A
0 M
B
F
1 M
F =A·B+A·B M {M(A, 0, B), M(A, 0, B), 1}
A
0 M
B

A
1 M
F =A·B+B·C M(B, M(A, 1, C), 0) C
F
0 M
B
8 VLSI Design

Table 1: Continued.
Standard Boolean function Majority expression Function implementation diagram
A
C M
1

0 M
B
F
F = A·B+B·C+A·B·C M {M(B, M(A, C, 1), 0), M(A, M(B, C, 0), 0), 1} 1 M
A
0 M
B
C M
0

A
B M
C
F
0 M
F =A·B·C+A·B·C M {M(A, B, C), M(A, B, C), 0}
A
B M
C

A
0 M
C

A
F
F= B M M
M {M(A, C, 0), M(A, B, C), M(A, B, C)} C
A·B ·C +A·B ·C +A·B ·C

A
B M
C

A
B M F
F =A·B+B·C+A·C M(A, B, C)
C

A
B M
C
F =A·B·C+A·B·C+ F
M {M(A, B, C), M(A, B, C), C } C M
A·B·C+A·B·C
A
B M
C

Table 2: Switching voltage at output node V of the capacitance network.

Inputs Voltage at V node Majority Not

A B C VDD Carry
0 0 0 0V 1
0 0 1 VDD /3 1
0 1 0 VDD /3 1
0 1 1 2VDD /3 0
1 0 0 VDD /3 1
1 0 1 2VDD /3 0
1 1 0 2VDD /3 0
1 1 1 VDD 0
VLSI Design 9

Table 3: Channel width v/s MOS capacitor in 0.18 μm Tech.

Cap 2.89 fF 4.89 fF 6.89 fF 8.89 fF 10.91 fF

Width (W) μm 1.59 2.71 3.83 4.95 6.07

(a) (b)

Figure 12: (a) MOSCAP Majority Not function layout. (b) Static CMOS bridge (Majority function) layout.

NOR function. Contrary to this, decreasing the ratio makes VDD

the NAND function. The second method uses high-threshold
voltage (Vth ) transistors (MP1 & MN1) as shown in Figure 4.
Simulation results in Table 4 illustrate the comparison
of static logic gates with MOSCAP-based majority function, MP1
A B C
static and dynamic logic style.

4.5. Layout and Area Analysis of Majority Circuits. The layout B C

of Majority Not function (MOSCAP) and static CMOS
bridge-type Majority function circuits are shown in Figures
12(a) and 12(b), respectively, and the area is given in Table 5. Cap
A
The area of the MOSCAP Majority function (MOSCAP) Cap Sum
circuit is 50% less than that of the bridge type Majority B
function circuit. At low voltages (say 1 V) delay and power Cap
consumption is much more improved in comparison to the C
static one, and hence MOSCAP Majority function is more
reliable, power efficient with less occupation of chip area in Carry
VLSI circuit designing. By a perfect layout design, even more A
reduction in the area is possible and thus a more compact MNI
design can be implemented. B C

4.6. A Review of Majority-Function-Based Full Adder Topolo-

gies. As Table 6 exhibits, Sum is different at merely two places B C
with Majority Not function when inputs are 000 or 111. The
values of these two functions are not equal at A = B =
C = “0” and A = B = C = “1”. Therefore, we correct
these two states by using a pMOS and an nMOS transistor. Figure 13: Design methodologies for Majority-function-based full
These transistors must be arranged in a way that ensures the adder (MajFA1).
correctness of the circuit [39].
The basic logic design of a full adder includes two 3-input
NAND and NOR gates with Majority Not function inputs input state the Sum is obtained by the NAND and NOR gates,
as shown in Figure 13. The MajFA1 adder is designed using respectively. In order to design circuit operations in the given
pass-transistor logic as shown in Figure 13 similar to the state one nMOS and one pMOS pass transistor are added to
[39]. The logic (NAND and NOR) gates designed with pass the circuit. These transistors are used to disconnect the path
transistor logic styles have less power dissipation and delay between Carry and Sum in all “0” and “1” input state.
than in standard CMOS.
In six mid-states of Table 6, the Sum output is equal 4.7. Majority Full Adder Using 3-Input Majority Not Function
to Carry (Majority Not Function) and the MP1 and MN1 (MOSCAP). In this section full adder based on low power
transistors are off. But, in all one input state and all zero design of 3-input Majority Not function (MOSCAP) with
10 VLSI Design

Table 4: Simulation results of NAND, NOR, and majority Not logic gates at 1 V.
Static Majority function MOSCAP Majority function
Design
Delay (ps) Power (μw) PDP (10−18 j) Delay (ps) Power (μw) PDP (10−18 j)
NAND 36 0.041 1.47 23 0.038 0.87
NOR 40 0.042 1.68 27 0.039 1.05
Maj. Not 43 0.048 2.06 18 0.038 0.68

Table 5: Simulation layout comparisons of Majority function logic.

μm Bridge Majority function MOSCAP Majority function

Length Width Area Length Width Area
Layout
(μm) (μm) (μm2 ) (μm) (μm) (μm2 )
Dimen. 8.8 6.9 60.7 9.9 2.95 29.2

standard logic gates is discussed. The Boolean expression Reference [42]. MajFA4 full adder design has two stages.
may be expressed as Carry is implemented by means of a Majority Not function
in the first stage and in the second stage a five-input Majority
Sum = Carry · (A + B + C) + A · B · C. (5) Not function is used for implementing Sum function.
In the full adder circuit shown in Figure 15, first Majority
Carry logic output will be generated by 3-inputs MOSCAP Not gate is made of 3-input MOSCAP with a CMOS
Majority Not function. inverter. Three Cap1 capacitors with input signal and CMOS
The MajFA2 full adder uses 12 transistors, and 3 capac- inverter are used to generate Carry signal. These three
itors are based on pseudo CMOS structure with MOSCAP input capacitors prepare an input voltage that is applied for
Majority function. Full adder output Carry function is driving CMOS inverter. If more than two inputs become
designed with 3 input Majority Not function logic. In this high then the M1 transistor will turn-on and in this case
design, “a” and “b” inverters implement NOR and NAND the Carry will fall to “0” logic. Therefore, Carry will be “1”
functions, respectively. logic. Otherwise, M1 and M3 will turn-off and turn-on,
The full adder (MajFA3) is based on MOSCAP Majority respectively, and output Carry will fall to “0” logic. Second
Not function with only static CMOS inverter as shown in Majority Not function is based on five-input capacitors
Figure 14(b). Simulation results illustrate that the reported and CMOS inverter (M2 & M4 transistors). It has two
adder circuits having low PDP works efficiently at low capacitors Cap2 and three inputs Cap2. Based on function,
voltages [41]. Outputs of the circuit will be connected to Sum = Maj(A, B, C, Carry, Carry), the value of Cap2 is
power supply or ground and therewith, the circuit has good two times the value of Cap1, because we are providing two
driving capability. These inverter-based full adders are a Carry as inputs with two parallel capacitors, and these two
suitable structure for the construction of low-power and capacitors are added. One 2 × Cap2 capacitance is attached
high-performance VLSI systems. between Carry output and input of transistor M2. The basic
scheme of this full adder circuit utilizes only 7 capacitors
and 8 transistors. The main advantage of this design is
4.8. Majority Full Adder Using 5-Input Majority Not Function its simplicity, modularity, and lesser number of transistors
(MOSCAP). Here if we exert a Majority function of five being used.
inputs out of which two are Carry and the other three are As reported in MajFA5, hybrid full adder circuit in
logic inputs (A, B, C), we will get Sum of the output as Figure 16 uses 16 transistors. Its output Sum function is
explained in the given equation. Consequently, according based on 5-input Majority Not gates. In this design, the first
to this fact Sum is generated by means of two Majority Majority Not gate is implemented with a high-performance
Not functions. The first one is a three input Majority Not CMOS bridge circuit [43]. This design uses more transistors,
function which results in the Carry function and the second called bridge transistors, sharing transistors of different
one is a five-input Majority Not function which creates Sum: paths to generate new paths from supply lines to circuit
outputs. The bridge design offers more regularity and higher
Sum = ABC + A BC + ABC + AB C performance than the other CMOS design styles and is
  completely symmetric in structure. Using the bridge circuit
= ABC + AB · AC · BC · (A + B + C) leads to reduction in delay and power consumption of the full
adder cell and it also increases the robustness of the circuit.
= ABC + Carry · Carry + Carry (A + B + C)

= ABC + Carry (AB + AC + BC) + Carry (A + B + C) 5. Proposed Hybrid Full Adder Topologies
 
= Majority A, B, C, Carry, Carry . 5.1. XOR-XNOR- (3T-) Based Full Adders. The general
(6) structure of a XOR-based full adder consists of one exclusive
VLSI Design 11

Table 6: Truth table for Majority-function-based full adder.

Inputs Full adder logic outputs
A B C Carry Carry Sum = Maj(A, B, C, Carry, Carry)
0 0 0 0 1 0
0 0 1 0 1 1
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 1 1
1 0 1 1 0 0
1 1 0 1 0 0
1 1 1 1 0 1

VDD
VDD
MP1
Cap
Sum A

NAND
Cap Sum
B

Cap
A NOR Cap
C
Cap
B MN1
Carry
Cap Carry
C
1
(a) (b)

Figure 14: (a) Majority-function-based full adder (MajFA2). (b) Inverter-based Majority full adder (MajFA3).

VDD VDD

Cap2 M3 M8
A C A
Cap2
B Carry
Cap2 Cap
C
M1 2xCap1 M7 A
B B C Cap
B Sum
VDD 2Cap
Cap
A
Cap1 M4 M6 C A C VDD
Cap1
B Sum
Cap1
C Carry
M2 M5 B C
B

Figure 15: 3-input MOSCAP Majority full adder (MajFA4). Figure 16: 5-input MOSCAP Majority full adder (MajFA5).

OR/NOR function (XOR/XNOR), two transmission gates degrades the drivability of cells designed with certain logic
in the middle, and one XOR gate to the right as shown in styles. By selecting proper (W/L) ratio, we can optimize
Figure 17. The complementary outputs of the XOR/XNOR the circuit performance parameters without decreasing the
gate are used to control the transmission gate which together power supply. The 3T XOR/XNOR gates are used in a
realizes a multiplexer circuit producing the carry. designed full adder circuits as shown in Figures 18 and 19.
The circuit is a combination of two logic styles and offers In design1 full adder circuit, XOR circuit comprises M1,
high-speed, low-power consumption and energy efficiency. M2 and M3 transistors and the output of M4 and M5
Lowering the supply voltage appears to be a well-known transistor is XNOR circuit. TG (M6, M7) and TG (M8, M9)
means of reducing power consumption. However, lowering give the carry and restored output swing. TG (M10, M11)
the supply voltage also increases the circuit delay and and pass transistor M12, M13 are used for Sum output
12 VLSI Design

C design significantly. In the reported previous full adder

XOR Sum
logic design [43], the CMOS bridge circuit does not have high
driving power to drive the capacitor (2Cap) and an inverter.
This increases the delay at low voltages in nanotechnology.
H However, in the proposed design, an inverter with high
B TG
XOR driving power drives four transistor gates (bridge circuit)
A logic H
XNOR Carry and an inverter. Besides, the more driving power of the
inverter in comparison to the bridge circuit and the sum of
the gate capacitances of four transistors being less than the
TG capacitance of the capacitor (2Cap) of the reported design
(MajFA5) illustrate the superiority of the proposed full adder
design (PMajFA1).
Figure 17: General structure of proposed XOR-XNOR-based adder. Furthermore, as in the proposed design three capacitors
perform voltage summation to implement scaled-linear sum
instead of five capacitors. It has larger noise margins than
B A VDD the previous design. Moreover, the proposed design have no
threshold loss problem at its nodes and has higher noise
margin compared to MajFA3 (minimum no of transistor)
M2 M3 M4
B M12 because its inverters has normal VTC curve, which works
M8 M10 on inverters with shifted VTC and its operation is highly
M6
C
dependent on the proper operation of these inverters.
A Sum The Majority-function-based proposed design 2 (PMa-
A
jFA2) adder uses 15 transistors and is based on regular
C dynamic CMOS bridge transistors. Full adder output Carry
M7 M9 M11
M1 M5 M13
function is designed with 3-input Majority Not function
Carry logic and output Sum function is generated using dynamic
CMOS bridge logic style as shown in Figure 21. The
advantage of these adder cells are higher speed, lower
transistor count and it compromises noise margin. This
type of circuit is preferred in smaller area requirement with
Figure 18: XOR- (3T-) based design 1 full adder. lesser delay at low voltage. It has larger noise margins in
comparison to the previous designs and reported full adder
circuits.
and to restore the output swing as shown in Figure 18. It
implements the complementary pass-transistor logic to drive 6. Simulation Results
the load.
A novel 16-transistor full adder circuit that generates The simulation has been performed for different supply volt-
XOR-XNOR outputs simultaneously is shown in Figure 19. age ranging from 0.8 V to 1.8 V, which allows us to compare
Similarly in design 2 full adder circuits M1, M2 and M3 are the speed degradation and average power dissipation of the
used as XOR and the output of M4, M5, M6 is XNOR circuit. reported and newly designed adder topologies. The results
The cross-coupled PMOS transistors are connected between of the designed circuits in this paper are compared with
XOR and XNOR output to alleviate threshold problem for a reported standard CMOS full adder circuit. To compare
all possible input combination at low voltage (0.8VDD ) and one-bit full adder’s performance, we have evaluated delay
reduce short-circuit power dissipation. The cross-coupled and power dissipation by performing simulation runs on a
two pMOS transistors (M7, M8) are connected between XOR Cadence environment using 0.18-μm CMOS technology at
and XNOR outputs to eliminate the nonswing operation at room temperature.
low voltage. The simulation test bench used for load analysis is shown
in Figure 22. Output loads have been added according to the
5.2. Majority-Function-Based Full Adder. In the proposed test bench. The two inverters with same W/L have been used
methodology, we have designed two full adder topologies, to make output buffers. Output load was added at the input
one is based on static bridge logic style and other is based of the output buffers to evaluate driving capability of the
on dynamic bridge logic style. The proposed adder modules circuits without output buffers. We used buffers to check the
enjoy advantages of the bridge style including low-power output logic levels. Power and delay of inverters have been
consumption and the simplicity of the design. The proposed included in power and delay calculation of the whole circuit.
full adder structure design (PMajFA1) is based on capacitor The transistor size for buffers is two for pMOS and one for
network and Majority Not function as shown in Figure 20. nMOS.
The proposed Majority-function-based adder design has The transistors that are used in XOR-XNOR- (3T-) based
some advantages which improves the metrics of the proposed full adder designed circuits (13T & 16T) are using 3T
VLSI Design 13

B A VDD

M2 M3 B M8
A
M10 M11 M14 C M15
M1
A Sum
VDD
VDD A
M9 M12 M13 M16
M5 M6 B M7 Carry
A

M4

Figure 19: XOR-XNOR- (3T-) based design 2 full adder.

VDD

Sum Buffer
C N
Cload 1fF
Adder cell
Cap circuit
A B
N A Sum
Cap
B Carry Buffer
Cap B
C Cload 1fF
Carry
C N
A

Figure 22: Simulation test bench for load Analysis.

Figure 20: Majority-function-based adder design 1 (PMajFA1).

VDD
when low power and high speed operation are needed. At low
MP1
voltages, design 1 is better than 9T and design 2. From the
simulation results, it is perceptible that design 1 is superior
Sum in PDP to all the other designs at all simulation conditions.
Cap A
A N
B Each one-bit full adder has been analyzed in terms
B
Cap N of propagation delay, average power dissipation, and their
C N products. By the value of delay, power, power-delay product
Cap
C Carry and energy delay product of C-CMOS, hybrid and newly
Clock MN1 designed full adders are measured. The smallest voltage
that could work on 10T is 1.4 V. The lowest supply voltage
for simulation comparison for conventional CMOS, and
Figure 21: Majority function-based adder design 2 (PMajFA2).
newly designed full adder circuits, is 0.8 V (VDD ). For each
transition, the delay is measured from 50% of the input
transistors XOR logic. Thus the area overhead of the designed voltage swing to 50% of the output voltage swing. The
circuits is lower than that of the reported conventional maximum delay is taken as the cell delay.
adders and also some other adder circuits. By optimizing High speed of the designed full adders is due to the short
the transistor size of full adders considered, it is possible path between input and output logic circuit. Simulation
to reduce the delay of all the adders without significantly results (Figure 23(a)) show that design 2 is the best circuit
increasing the power consumption, and transistor sizes can in terms of speed at all voltages since XOR and XNOR logic
be set to achieve minimum power delay product (PDP) and is generated separately in a single circuit. It has high delay
energy delay product (EDP). All adders were designed with and high sensitivity against voltage scaling. Design 2 is miles
minimum transistor sizes initially and then simulated. The ahead than design 1 and shows better performance even
PDP (10−18 j) and EDP (10−30 sj) are a quantitative measure than 9T full adder. At low voltages, design 2 shows better
of the efficiency and a compromise between power dissipa- delay than 9T. 9T has minimum number of transistors but
tion and speed. PDP and EDP are particularly important high delay because XNOR logic is generated using XOR with
14 VLSI Design

100
10
90
80
8
70

Power (×E−06)
Delay (×E−12)

60 6
50
40 4
30
20 2
10
0 0
0.8 1 1.2 1.4 1.6 1.8 0.8 1 1.2 1.4 1.6 1.8
Voltage (V) Voltage (V)

C-CMOS Design 1 C-CMOS Design 1

9T 9A (10T) 9T 9A (10T)
14T Design 2 14T Design 2
(a) (b)

Figure 23: (a) Delay (ps) of XOR-XNOR-based adders. (b) Power (μW) XOR-XNOR-based adders.

Power versus supply voltage

Delay versus supply voltage 60
0.8

0.7
45
0.6
Power (µw)

0.5
Delay (ns)

0.4 30

0.3

0.2 15

0.1

0 0
1 1.2 1.4 1.6 1.8 1 1.2 1.4 1.6 1.8

Bridge (24T) MajFA2 Bridge (24T) MajFA2

MajFA4 PMajFA2 MajFA4 PMajFA2
MajFA1 MajFA3 MajFA1 MajFA3
PMajFA1 PMajFA1
(a) (b)

Figure 24: (a) Delay of Majority-function-based full adder circuits. (b) Power of Majority-function-based full adder circuits.

CMOS inverter. However, at all supply voltage variations in terms of speed at all voltages. It has low delay and high
Design 2 is faster than 9T full adder. sensitivity against voltage scaling. Design 2 is miles ahead
Figure 23(b) shows that proposed design 2 full adder is than the reported design and shows better performance.
the most power consuming circuit at 1.8 V. The power con-
sumption worsens as we increase the supply voltage. Design 1 6.1. Load Analysis. Output load is one of the important
has the least power consumption in comparison to the other parameters that affects power and performance of the
simulated adder circuits. It worked successfully even at low circuits. Here we changed the output loads from 2 fF to
voltage. Design 2 full adder consumes higher power due to 500 fF. A fixed value 1 fF capacitance has been added at the
the use of high power consuming 3T XOR and a 3T XNOR output of the buffer circuit. Minimum output load for all
gate in a single unit. the simulation is 2 fF, except for the case in which we study
Simulation results (Figure 24) show that Majority func- the effect of output load on full adder. The effect of output
tion based design 2 full adder (PMajFA2) is the best circuit load is shown in Figures 25 and 26. All the circuits have been
VLSI Design 15

PDP and EDP with load cap. 2 fF PDP and EDP at load cap. 500 fF
6800 600

5800 500
4800
400
3800
300
2800
200
1800

800 100

−200 0
PDP (×E−18) EDP (×E−28) PDP(×E−15) EDP(×E−24)

C-CMOS Design 1 C-CMOS Design 1

TG Design 2 TG Design 2
9T 9T
(a) (b)

Figure 25: (a) PDP and EDP of XOR-XNOR based full adder cells with load capacitance (2 fF) at 1.8 V. (b) PDP and EDP of XOR-XNOR
based full adder cells with load capacitance (500 fF) at 1.8 V.

PDP versus load capacitance (2 fF–10 fF) at 1V

6

5
PDP versus load capacitor (2 fF–10 fF) at 1.8V
60
4
50

40 3

30
2
20
1
10

0 0
2 4 6 8 10 2 4 6 8 10
(fF) (fF)
MajFA1 PMajFA1 MajFA1 PMajFA1
MajFA2 PMajFA2 MajFA2 PMajFA2
MajFA3 MajFA3
(a) (b)

Figure 26: (a) PDP comparison of Majority-function-based full adder cells with capacitance load variation at 1.8 V. (b) PDP comparison of
Majority-function-based full adder cells with capacitance load variation at 1 V.

optimized at 1.8 V supply voltage with 2 fF output load. For shown in Figure 25, design 1 has the lowest PDP for all
fair comparisons, the conditions were kept unchanged for all output loads below 500 fF. In the case of 500 fF output load,
circuits. 9T shows huge improvement in terms of PDP in comparison
9T is the best circuit in terms of power consumption to the other designed circuits. At 2 fF, 9T has better EDP than
since it has the least power consuming for all values of output all other designed circuits. As shown in Figures 25 and 26,
load. The power of the designed circuits changes sharply by design 1 has lowest EDP in all output loads below 500 fF. In
increasing the output load capacitance value as shown in case of 500 fF output load, 9T has the lowest EDP. Design 2
Table 3 at 1.8 V. At 2 fF load, design 2 is the fastest circuit. shows improvement in terms of EDP in comparison to the
Design 2 full adder is, however, placed second after 9T in other circuits at maximum load condition. At all output load
terms of delay in high output load capacitance 500 fF. As values, 9T is better than design 1 in terms of EDP.
16 VLSI Design

Table 7: Area comparisons of the XOR-XNOR-based adders.

Designs CMOS TGA 10T 9T Design 1 Design 2
Length (μm) 17.5 14 11.2 10.1 15.5 15.2
Width (μm) 7.1 9.6 6.3 8.2 5.15 6.6
Area (μm2 ) 124.2 135 71 82.8 80 100.3

(a) (b)

Figure 27: (a) Layout of design 1 (13T) full adder cell. (b) Layout of design 2 (16T) full adder cell.

(a) (b)

Figure 28: (a) Layout of design 1 (PMajFA1) full adder cell. (b) Layout of design 2 (PMajFA2) full adder cell.

Majority-function-based design 1 full adder (PMajFA1) most number of metal lines to connect the complementary
is the best circuit in terms of power consumption for all inputs. 10T adder has the lowest area because of the number
values of output loads. The power of the designed circuits of transistors, but the overall performance is inferior at low
changes sharply by increasing the output load capacitance supply voltage (less than 1.4 V). The compact designed layout
value at 1 V. At 2 fF load, Design 2 full adder (PMajFA2) is of the newly design full adders using 0.18 μm technology is
the fastest circuit. According to the simulation results, design all shown in Figures 27 and 28. The layout of the design 1
1 (PMajFA1) and design 2 (PMajFA2) has the lowest PDP circuit occupies the least silicon chips area amongst all the
among the other circuits for all output load capacitors as simulated full adder cells that are performed well below 1 V.
shown in Figure 26. The schematic and layout editors are Cadence Virtuoso and
Cadence Virtuoso XL, respectively, which are used for layout
6.2. Layout and Area Analysis. With regard to the imple- designing.
mentation area obtained from the layouts, it can be seen The values of layout circuit length, width, and overall
that the proposed full adders require the smallest area, area are listed in Table 7. Simulation layout results show
which can also be considered as one of the factors for that design 1 has the minimum power consumption due to
the lower delay and power consumption, as it implies the lowest area. 9T has minimum number of transistors but
smaller parasitic capacitances being driven inside the full its area is much more due to the optimization of transistor
adder. Table 7 illustrates that the layout of TGA full adders parameter (W/L) which works at low voltage. Power con-
occupies the maximum silicon area. TGA adder is composed sumption is lower than the 10T full adder and it can work up
of transmission gates, which has more area due to the to 0.8 V satisfactorily. Design 2 has highest power dissipation
inefficient usage of the n-type wells. CPL adder needs the when compared to the other designed full adder circuits. By
VLSI Design 17

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