6192 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO.

9, SEPTEMBER 2016

Challenges Facing PFC of a Single-Phase On-Board

Charger for Electric Vehicles Based on a Current
Source Active Rectifier Input Stage
Christelle Saber, Student Member, IEEE, Denis Labrousse, Bertrand Revol, Member, IEEE, and Alain Gascher

Abstract—This paper aims to study the power factor (PF) correc-

tion scheme for a single-phase on-board charger of electric vehicles.
The topology is based on a unidirectional current source active rec-
tifier (CSAR) consisting of four insulated-gate bipolar transistors
in series with four diodes followed by a boost converter. Buck-
type rectifiers inject low-order input current harmonics into the ac
mains. Thus, an inductor–capacitor (LC) input filter is employed.
The capacitor’s reactive energy results in a leading grid current. In
order to achieve a unity displacement power factor, a phase shift
control is implemented. However, the LC filter is prone to series
and parallel resonances coming from the grid disturbances and the
converter harmonics, respectively. Therefore, the phase shift con-
trol strategy combined with the topology of the CSAR results in a
periodical resonance of the input filter. This phenomenon is stud-
ied in detail. In order to reduce the grid current’s distortion level, Fig. 1. Power circuit of the three-phase integrated charger with a CSAR input
stage and the traction inverter used as a dc/dc voltage step up converter output
an active damping control with resonance frequency tracking that stage.
achieves a good PF while meeting the IEC’s international standards
on harmonic current emissions is presented. An experimental test
bench is developed to validate the simulations’ theoretical findings.
Compliance with the standards is achieved and system limitations
are discussed.
Index Terms—Battery charger, current source active rectifier
(CSAR), electric vehicle (EV), filter resonance, frequency track-
ing, phase shift control, power factor correction (PFC), self-tuning
active damping.

I. INTRODUCTION
ATTERY chargers for electric vehicles (EVs) are classified
B as on-board or off-board chargers [1]. Off-board chargers
are not constrained by size or weight but introduce additional Fig. 2. Power circuit of the single-phase charger with a CSAR input stage, a
cost to the infrastructure through the deployment of a high num- freewheeling diode, and a dc/dc boost output stage.
ber of charging stations. In order to meet the needs of EV users
in terms of charging availability, on-board chargers that achieve the parts of the traction power train for charging, the latter re-
ac/dc conversion are retained. Furthermore, on-board chargers duces the cost of the charger. Disadvantages of integrated sys-
are classified as standalone or integrated systems [2]. By reusing tems include electromagnetic compatibility issues and complex
control schemes.
Manuscript received July 6, 2015; revised September 22, 2015; accepted The topology studied in this work is an ac/dc on-board
November 2, 2015. Date of publication November 17, 2015; date of current integrated charger for EVs that can accommodate 43-kW three-
version March 25, 2016. This work was supported by Groupe Renault through
an industrial Ph.D. dissertation. Recommended for publication by Associate phase fast charging (see Fig. 1) as well as 1.8 to 7.2-kW
Editor M. Ordonez. single-phase residential charging (see Fig. 2). Since this study is
C. Saber is with Renault S.A.S, Laboratory of Systems and Applications conducted for the automotive industry, cost, size, and security
of Information and Energy Technologies, Cachan 94235, France (e-mail:
[email protected]). requirements related to these types of chargers constitute ma-
D. Labrousse is with the Conservatoire National des Arts et Métiers, Paris jor design constraints. Cost and size reductions are achieved
75003, France (e-mail: [email protected]). through the integration of the traction inverter as well as the
B. Revol is with the Ecole Normale Supérieure de Cachan, Cachan 94235,
France (e-mail: [email protected]). electric machine windings into the charging power circuit as
A. Gascher is with Renault SAS, Guyancourt 78288, France (e-mail: shown in Fig. 1. Usually, an interleaved boost control presents
[email protected]). several advantages among which a better distribution of the
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. thermal losses, higher system reliability, and reduction of
Digital Object Identifier 10.1109/TPEL.2015.2500958 the ripple on the input as well as the output signals of the
0885-8993 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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 SABER et al.: CHALLENGES FACING PFC OF A SINGLE-PHASE ON-BOARD CHARGER FOR ELECTRIC VEHICLES 6193

converter. However, our topology utilizes the electrical machine for the damping resistor, in our case, is in parallel to the input
windings as filtering inductors. Therefore, the boost legs are capacitor. Single-phase on-board charging of EVs is dedicated
not interleaved but rather synchronously controlled to form an for residential charging stations. However, the variability of the
equivalent one-legged boost converter as in Fig. 2. This yields grid’s impedance from one charging station to the other leads to
a dc/dc voltage step-up output stage. In order to accommodate the variation of the resonance frequency.
a wide input voltage range and a varying dc voltage output, So far, grid impedance estimation methods vary from using
the input stage of the converter is a current source active rec- control loops to provoke a controlled input filter resonance and
tifier (CSAR) with voltage step-down capability. It consists of estimate resistive and inductive parts of the grid [15] to meth-
four insulated-gate bipolar transistors (IGBTs) placed in series ods using noncharacteristic interharmonic injection signals [16]
with four diodes in order to ensure reverse blocking capabil- and methods using extra devices for grid impedance estimation
ities. Despite their challenging control structures compared to [17]. On another hand, a noninvasive method based on extended
voltage source topologies, current source rectifiers present ma- Kalman filter was proposed in [18]; however, this method re-
jor security advantages because of their capability of limiting quires computational efforts. The novelty in this paper consists
the inrush currents, when the input filtering capacitor is small of making use of the input filter’s periodical resonance to esti-
enough, as well as the dc short-circuit currents [3]. This paper mate the grid’s impedance. For that reason, an online discrete
focuses on the challenges facing power factor correction (PFC) Fourier Transform (DFT) algorithm based on a running sum-
for the single phase configuration (see Fig. 2). mation is developed to track the resonance frequency and adjust
The rectifier’s switching takes place on the input side; there- the damping resistor value online during charging. This results
fore, a passive inductor–capacitor (Lf , C) filter needs to be in a self-tuning AD scheme.
employed. This filter is usually designed in the literature to A brief description of the charger’s current control structure
have a cutoff frequency that ensures the required attenuation is presented in Section II. Emphasis is then brought to the CSAR
for the first input current harmonic [4]. In that way, the current and the phase shift DPFC strategy. The switching states of the
harmonics will be sufficiently attenuated and the parallel filter input stage are studied at each zero crossing of the ac mains.
resonance excited by the switching harmonics avoided. How- This comprehensive analysis shows the presence of zero levels
ever, the charger maintains the traction’s switching frequency at in the converter current which could eventually excite the in-
10 kHz. This would result in a low filter cutoff frequency and a put filter’s resonance. Simulation results validate the theoretical
large sized filter. For that reason, only a differential mode (DM) analysis by showing an oscillation at each zero crossing of the
inductor Lf is placed in series with the grid impedance. mains voltage. This phenomenon is analyzed in Section III. An
It is designed for high-frequency attenuations and the capac- AD solution based on a virtual resistor placed in parallel with
itor is added to ensure proper filtering of the switching compo- the filter’s capacitor is applied in Section IV in accordance with
nent; therefore, the filter’s cutoff frequency is around 2 kHz and an online DFT to track the resonance frequency variations. Ex-
remains insufficient for proper filtering of the low-frequency perimental validation on a laboratory prototype and compliance
current harmonics defined by the standards. The capacitor’s re- with the standards are provided in Section V. Finally, system
active energy results in an input current that is leading the grid’s limitations are discussed in Section VI.
voltage; hence, displacement power factor correction (DPFC)
is needed. Various power factor control schemes have been de- II. DISPLACEMENT POWER FACTOR CORRECTION
veloped; some are based on reactive energy compensation [5],
The challenges of achieving unity power factor mainly result
[6] and others on direct phase shift control [7], [8]. However,
from using the CSAR as the charger’s input stage. Therefore,
given the fact that our input stage is a unidirectional active
the grid side of the converter is the main focus of this paper. In
rectifier, the structure retained is based on phase shift control.
order to highlight the effects of the DPFC on the input side of
Simulation results show a periodical resonance phenomenon
the charger, the current in the filtering inductance of the boost
that appears on the grid side of the converter. Previous works
is controlled at a constant level by using a hysteretic current
using single-phase CSARs [9], [10] mainly study the control
controller. Hence, the CSAR is studied with the equivalent of a
schemes under grid voltage distortion. However, the distortion
current source output stage (see Fig. 3).
appearing when using phase shift has not yet been analyzed with
respect to the excitement of the input filter’s resonant mode.
In this paper, we highlight an input filter resonance due to the A. Analysis
single-phase DPFC scheme. Several methods for resonance har- Fig. 4(a) shows the natural phasor diagram of the angular
monic mitigation have been studied in the literature [11], [12]. line frequency components on the input side of the converter.
Harmonic injection methods, notch filtering that compensates The grid-side voltage sensor measures the voltage across the
the resonance frequency gain, lead/lag phase compensators, as filter capacitors; therefore, vc is chosen as the phasor diagrams’
well as selective harmonic elimination techniques are widely reference signal. A PFC converter is usually operated so as to
employed. However, most of these methods require calibration draw a converter current if with a fundamental component being
efforts and extra sensors. In order to enhance the quality of the in phase with the converter voltage vc [see Fig. 4(b)]. However,
current drawn from the grid, an active damping (AD) solution the latter causes reactive current ic to flow through the input
is proposed. Liserre et al. [13], [14] study different AD sce- capacitor. Consequently, the current ig drawn from the grid, at
narios for three-phase active rectifiers. The optimal placement the charging station, is naturally leading the input voltage by

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 6194 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016

Vector-based single-phase PLLs are inspired from the three-

phase synchronous frame PLLs. However, the challenge in
single-phase applications consists of generating a signal with
a 90° phase shift with regards to the input fundamental. Let x
represent an electrical variable such as a grid current or voltage
∞

x (θx ) = X1m sin (θx + ϕ1x ) + Xn m sin (nθx + ϕn x ).
n =2
(1)
The role of the SOGI (see Fig. 5) is to compute a virtual two-
Fig. 3. Equivalent power circuit of the single-phase charger with a hysteretic phase stationary orthogonal reference frame (α, β) in which the
current controller applied to the boost output stage.
input signal’s components (xα , xβ ) are found through the use
of two integrators. The filter’s transfer functions are computed
in (2) and (3). It can be seen from (4) that xβ has a 90° phase
shift with regards to xα . The latter represents the fundamental
component of x. Their expressions are given in (5) and (6)
xα Ksogi × ωpll × s
(s) = 2 (2)
x s + Ksogi × ωpll × s + ωpll
2

Fig. 4. Current and voltage phasor diagrams at the grid side when having a xβ Ksogi × ωpll
2
(s) = 2 (3)
constant dc current and If = IL . (a) Natural extended phasor diagram before x s + Ksogi × ωpll × s + ωpll
2
PFC. (b) Simplified typical PFC configuration showing a phase lead of the grid
current. (c) Simplified proposed PFC scheme based on the phase-lag of the xβ ωpll
converter current. (s) = (4)
xα s
xα = X1m sin (θx + ϕ1x ) (5)
the displacement angle ϕ; this results in a reduced displacement
power factor (DPF), defined as DPF = cosϕ, and a reduced xβ = −X1m cos (θx + ϕ1x ) . (6)
power factor.
The design of such a capacitor is highly dependent on On the other hand, the role of the PLL is to extract the in-
the switching frequency and the charging power. Moreover, formation regarding the angular frequency (ωpll ) as well as the
it should meet several requirements among which a size information regarding the amplitude of x. By substituting (5)
constraint, a sufficient attenuation of the switching compo- and (6) into the rotation matrix expression (7), we can easily
nent, as well as achieving control stability by limiting the fil- deduce that xd yields the information regarding the amplitude
ter/converter interactions [19]. One additional requirement that of x as in (9). On the other hand, substituting (8) and (10) into
should be taken into consideration only when designing PFC the PLL’s closed loop with a null reference leads to (11)
converters is the maximum allowed displacement angle between
the filter’s input voltage and current introduced by the capacitor. xd = xα cosθpll + xβ sinθpll (7)
Whenever this design constraint is not met, the need for DPFC xq = −xα sinθpll + xβ cos θpll (8)
manifests itself.
xd = X1m (9)
ωpll
B. Grid Synchronization Using Second-Order Generalized θpll = (10)
s
Integrator (SOGI) Phase-Locked Loop (PLL) Scheme
π
PFC applied to an active rectifier requires the extraction of θpll = θx + ϕ1x − . (11)
2
information from the voltage supply in order to synchronize the
Synchronization between the SOGI and PLL is achieved
control with the line frequency. This is usually achieved through
through feedback of ωpll . Assuming that the grid has a ref-
the use of either closed-loop or open-loop methods [20]. The
erence frequency of ω ∗ = 2π × 50(rad · s−1 ) that can slowly
latter include DFTs [21], Kalman filtering techniques [22], adap-
vary between 48 and 52 Hz, the PLL is able to track the real an-
tative notch filtering methods, and weighted least mean square
gular frequency ωpll by adjusting the reference frequency value
algorithms [23]. However, their performances are highly depen-
ω ∗ through the proportional-integral (PI) controller output.
dent on their ability to filter distorted signals as well as their
adaptability to changes in frequency. On the other hand, closed-
C. Phase Shift Control Scheme
loop methods are based on PLL whether in their classical defi-
nition or modified structures [24]–[27]. Among those methods, In order to compensate for the input capacitor’s reactive en-
the SOGI-PLL allows the filtering of the input signal without ergy, a forced phase lag of an angle α is introduced to the
introducing phase delay and presents adaptative capabilities to converter current if . Thus, a lagging if will compensate for
frequency variations [28]. a naturally leading ig , as shown in Fig. 4(c). The use of the

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 SABER et al.: CHALLENGES FACING PFC OF A SINGLE-PHASE ON-BOARD CHARGER FOR ELECTRIC VEHICLES 6195

Fig. 5. Generalized SOGI-PLL synchronization block diagram.

Fig. 7. Open-loop response to a step-like variation of phase angle α. Ch1:

T1H gate signal. Ch2: phase angle α of converter current if . Ch3: Converter
voltage v c and Ch4: phase angle ϕ of grid current ig .

frequency ωpll and the displacement angle ϕpll between these

Fig. 6. DPFC scheme based on phase shift control.
two signals is extracted using two PLLs. The control scheme
must compensate the total input reactive energy, including any
future EMI filter adopted and its additional capacitors. There-
CSAR as an input stage presents the advantage of being able to fore, the phase lag angle α is not mathematically computed using
shape the fundamental component of the converter current if a known capacitance value; it is, however, deduced from a phase
and introduce the required phase lag. shift control loop. Furthermore, for the sake of simplicity, the
PWM linear control of current rectifiers based on PI con- maximum converter current is equal to the dc current iL . How-
trollers varies depending on the control strategy employed [29]. ever, in order to ensure the possibility of achieving unity DPF,
Three main strategies are distinguished: current control [30], ac- both simulations and experimental validations employ values
tive/reactive power control [31], [32], and direct phase control for iL that comply with
[33]. PIs used in PFC current control schemes present limited
disturbance rejection capability as well as a steady-state mag- IL ≥ ω (C/2) Vc . (12)
nitude and phase error since the reference signal is a sinusoidal Computation of the PI controller parameters is achieved
waveform in phase with the converter voltage. This leads to through the identification of the transfer function between the
higher current distortions and reduced DPF. On the other hand, grid current’s leading phase angle ϕ and the converter current’s
PI current controllers used in the synchronous dq-frame allow lagging phase angle α. The open-loop response to a step change
for separate active and reactive power controls as well as faster in α indicates that the transfer function (13) can be approxi-
dynamic response due to the constant dc nature of the reference mated by a first-order system (see Fig. 7). The time constant τi
signals. However, this strategy requires more computational ef- is chosen through pole placement and the proportional gain kp
forts from the digital signal processor (DSP) and the decoupling is tuned to ensure adequate time response
of the active/reactive powers requires the use of cross-coupling
ϕ k
terms dependent on the input filter parameters. Finally, the use (s)  (13)
of PI controllers in direct phase shift strategies is parameter α 1 + τs
 
independent. Furthermore, the phase reference signal is a dc τi s + 1
quantity. However, the closed loop is highly dependent on the PI(s) = kp . (14)
τi s
SOGI-PLL synchronization dynamics.
Fig. 6 shows the employed direct phase shift DPFC scheme.
D. Simulation Results
Current and voltage sensors are used at the power outlet level.
The fundamental components of the measured converter voltage Simulation results, for the system parameters provided in
vcα and grid current ig α are determined using the (SOGI) fil- Table II, are presented in Fig. 8. In order to emulate a current
ter described above. The information regarding the angular line source, the equivalent boost filtering inductor is deliberately
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 6196 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016

TABLE I
GRID-SIDE SYSTEM PARAMETERS

Symbol Description Value (Unit in SI)

Lg Grid impedance 50 (μH)→ 2 (mH)

Lf DM filter inductor 60 (μH)
C Series input capacitors 100 (μF)

Fig. 9. Bode gain plot (dB) of the admittance of the input filter for different
grid impedance values using Psim.
TABLE II
SIMULATION AND EXPERIMENTAL SYSTEM PARAMETERS

Symbol Description Value (Unit in SI)

C Series input capacitors 100 (μF)

Lg Grid impedance’s imaginary part 2 (mH)
Lf DM filter inductor 60√(μH)
Vg m Amplitude of the ac mains voltage 100 2 (V )
ω Angular line frequency 2π × 50 (rad/s)
IL Current level controlled by the boost 8.5 (A)
Leq Equivalent filtering inductor 2 (mH)
fs w Switching frequency 10 (kHz)
ϕ∗ Displacement angle reference 0°
fs Sampling frequency 10 (kHz) Fig. 10. Switching states of the input CSAR’s reverse blocking IGBTs.

noncompliance occurs for the harmonics surrounding the input

filter’s resonance frequency [see Fig. 8(d)]

 40 
  In RM S 2
THD% = 100 ×  (15)
n =2
I1RM S

1
fr =  . (16)
2π (Lg + Lf ) C

The frequency peak due to the resonance is particularly sen-

sitive to the grid impedance change (see Fig. 9), the filter’s
second-order oscillatory response appears on the input current
and converter voltage, respectively. Therefore, the grid-side dis-
tortion is a slightly damped periodical resonance phenomenon.

III. ANALYSIS OF THE RESONANCE PHENOMENON

A. Time-Domain Analysis
Fig. 8. DPFC simulation results. (a) Distorted converter voltage. (b) Converter
current presenting zero levels. (c) Current drawn from the grid. (d) Harmonic Experimental results shown in [6] also present a periodical
content of the grid current compared with the IEC standard up to 2 kHz. resonance at the beginning of each half cycle; however, this phe-
nomenon has not yet been investigated. In order to understand
chosen to be high enough to reduce the dc current ripple while the reason behind the excitement of the input filter, we will ex-
maintaining the same switching frequency. The theoretically amine the switching states of the CSAR. The low-side IGBTs
calculated total harmonic distortion (THD) level of the grid are maintained closed during charging and the diodes in each of
current is calculated using (15) and is found to be at 17%. the following pairs (D1H , D1L ) and (D2H , D2L ) have opposite
Results show a distortion occurring at each zero crossing of states. The switching of the diodes depends on the converter’s
the mains voltage as well as the presence of zero levels at the voltage polarity (see Fig. 10). However, the IGBTs’ switching
beginning of each half cycle of the converter current. states depend on the lagging converter current’s polarity. There-
Furthermore, the investigation of the low-frequency content fore, at each zero crossing of the mains voltage and as long as
of the grid current highlights the 7th harmonic (f11 = 350 Hz) if is lagging with respect to vc , the diodes will block the flow
as the harmonic with the highest amplitude. This odd harmonic of the converter current. This results in periodical zero levels
coincides with the input filter’s resonance frequency defined in in the converter current. On another hand, the LC input filter
(16). These results are going to be analyzed in the next sec- is prone to series and parallel resonances coming from the grid
tion. On the other hand, the comparison with the IEC61000 3-2 disturbances and the converter harmonics, respectively. Thus,
standard clearly shows that the charger with the present DPFC the periodical zero levels in the converter current presenting a
scheme is noncompliant with the limits defined; moreover, this rich low-frequency spectrum are sufficient to excite the filter’s
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 SABER et al.: CHALLENGES FACING PFC OF A SINGLE-PHASE ON-BOARD CHARGER FOR ELECTRIC VEHICLES 6197

dards. For that reason, an AD with resonance frequency tracking

solution is proposed.

A. Active Damping
In order to attenuate the input filter’s resonance, an obvious
solution would be the use of passive damping. However, the
extra physical resistor required leads to additional costs, higher
losses, and reduced efficiency. Therefore, AD control that uses
the rectifier in order to emulate the presence of a virtual resistor
is employed.
1) Effect on the DPFC Scheme: The placement of the virtual
damping resistor could vary between series and/or parallel to the
input filter’s inductor and/or capacitor. Several factors need to
be taken into account when choosing an optimal damping strat-
egy. Table III summarizes the differences between the various
possibilities in terms of sensors needed and control implemen-
Fig. 11. Input filter response for a converter current presenting only zero tation. For the application at hand, in order to make use of the
levels without switching component. (a) Converter current without switching
component. (b) Grid current as the input filter response. (c) Harmonic content sensors already employed to measure the grid current and con-
of the converter and grid currents. verter voltage, two configurations are possible: either in series
with the grid impedance or in parallel with the filter capacitor.
parallel resonant mode and produce a second-order oscillatory Based on control complexity, the optimal placement would be
response. in parallel with the capacitor which translates at the implemen-
tation level into a frequency invariant term to be added to the
B. Frequency-Domain Analysis control as opposed to the need for a differentiator [36].
Previous work [33] shows that the switching harmonics lead The virtual resistor (Rv ) placed in parallel with the input ca-
to the resonance of the input filter. The study deals with a three- pacitor reduces the current that is flowing into the capacitor by
phase CSAR based on gate-controlled thyristors switching at a value that is proportional to the converter’s voltage. We solely
low frequency 540 Hz. However, our study deals with a single- use the harmonic component of the capacitor’s voltage vch to
phase CSAR based on IGBTs switching at 10 kHz; hence, the compute the required damping current (see Fig. 12). This avoids
switching harmonics are shifted toward the high frequencies. the injection of an active power that will interfere with the cur-
Since the input filter’s resonance for 600-μH grid impedance is rent control. The harmonic extraction method needs to be insen-
of 619 Hz, nearly 16 times lower than the switching frequency, sitive to variations in the grid frequency. This is usually achieved
it is the DPFC scheme rather than the switching harmonics that in the dq-frame through high-pass filtering which eliminates the
leads to parallel resonance of the filter. In order to illustrate dc component [33]. The latter represents the fundamental of
that, a simulation is carried where we impose a converter cur- the signal; therefore, the remaining is the dq-component of the
rent presenting only periodical zero levels without pulse width harmonics. However, since our control scheme’s SOGI filter is
modulation (PWM) and study the low-frequency spectrum, up adaptive to frequency variations and introduces no additional
to 2 kHz, of both the converter and grid current (see Fig. 11). By delay to the extraction of the fundamental, the voltage harmon-
isolating the effect of the zero levels from that of the switching, ics are calculated by subtraction of the fundamental from the
we find that the converter current presents a rich low-frequency measured signal. Furthermore, a low-pass filter places an up-
spectrum with a 7th harmonic sufficient to excite the filter’s res- per limit on the voltage harmonic frequencies to be injected. In
onant mode. Therefore, the distortion is due to the zero levels order to respect the system dynamics and allow the carrier sig-
that excite the input filter’s resonance. nal to incorporate the harmonic frequencies in the pulse width
modulation process, those frequencies should be limited at least
IV. PROPOSED SOLUTION to one-sixth of the switching frequency. Fig. 13 shows the mod-
ifications brought to the previous DPFC to account for the AD
Power quality solutions are of great interest for electric car of the input filter’s resonance.
manufacturers. Battery chargers for EVs need to be compliant 2) Value of the Virtual Damping Resistor: The damped fil-
with the IEC’s international standards on electromagnetic com- ter’s transfer function is given in (17). The value of the virtual
patibility which define the limits for harmonic current emissions resistor is then computed in (18) using the resonance frequency
up to 2 kHz. Based on the charging power, two standards can be ωres and the damping factor ζ
distinguished. IEC61000-3-2 is designated for charging powers
that draw a RMS current lower than or equal to 16 A per phase ig (s) 1
[34]. On the other hand, IEC61000-3-12 defines the limits for = 2(L g +L f )
(17)
if (s) (Lg + Lf ) Cs2 + s +1
the levels of harmonic current rated from 16 to 75 A per phase Rv
[35]. The grid current’s distortion, as analyzed in the previous (Lg + Lf ) ωres
section, can lead to noncompliance with the above-defined stan- Rv = . (18)
ζ
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 6198 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016

TABLE III
COMPARISON BETWEEN DIFFERENT PLACEMENT SOLUTIONS FOR VIRTUAL DAMPING RESISTOR

able grid-dependant resonances. As shown in (18), the damping

resistors’ value is highly dependent on the grid’s impedance and
the input filter’s resonance.
3) Self-Tuning AD Based on an Online Running Summation
DFT: With the wide deployment of residential charging sta-
tions, EVs’ chargers need to maintain their stability and com-
pliance with the standards. However, the variability of the grid’s
Fig. 12. Block diagram of the damped input filter using the converter voltage impedance from one charging station to the other leads to the
harmonics. variation of the resonance frequency, and with it the variation
of the adequate damping resistor value.
The approach developed for the determination of this value
consists of finding the optimal damping for each detected res-
onance; as a result, the determination of the grid’s impedance
is required. Taking advantage of the periodical resonance phe-
nomenon appearing on the mains voltage, the proposed method
is an online DFT with a running summation that tracks the
resonance frequency variations.
The running summation principle was first introduced in
[37]; however, the approach was applied to a single known
interharmonic frequency corresponding to an external signal
injected into the system. The main disadvantage of such method
is related to the choice of the injection signal’s amplitude which
needs to be high enough to be detected but low enough so it does
not affect the overall system stability. The running summation
algorithm is a digital implementation of the well-known DFT
Fig. 13. AD combined to the DPFC scheme. expressions. Fig. 14 shows the general concept of the algorithm
with A and B being sampling time-dependent DFT coefficients.
Determination of the virtual resistor’s value is not an easy It consists of analyzing the harmonic content, up to the 40th
task. To the best of our knowledge, current methods [14] com- rank, of the measured grid current or converter voltage in
pute an optimal resistor value for different operating points. order to extract the rank of the harmonic presenting the highest
However, the resonances treated are due to known harmonics. amplitude. This harmonic is considered to be the closest
The novelty of this paper consists of studying the case of vari- multiple of the fundamental period to the actual resonance.

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 SABER et al.: CHALLENGES FACING PFC OF A SINGLE-PHASE ON-BOARD CHARGER FOR ELECTRIC VEHICLES 6199

Fig. 14. Online DFT algorithm based on a running summation and generating a self-tuning damping resistor value.

Fig. 15. Online DFT algorithm flowchart that shows the self-tuning capability
of the AD.

The algorithm’s described logic is presented as a flowchart in

Fig. 15. However, this renders the algorithm dependent on Fig. 16. Simulation results of the AD associated with resonance frequency
external grid disturbances with amplitudes higher than the tracking. (a) Converter voltage before and after AD. (b) Converter current pre-
senting zero levels. (c) Grid current before and after activation of the damping
resonance frequency’s. at 0.33 s. (d) Low-frequency harmonic content of ig without AD. (e) Low-
Two cases can be distinguished: frequency harmonic content of ig with AD.
1) Transient grid disturbances higher than the resonance:
The distinction between such distortions and the periodic Cosimulations between MATLAB and Psim are carried and
resonance of the input filter can be achieved through in- the results, with the system parameters of Table II are pre-
creasing the number of periods (widening the window) sented in Fig. 16 where the DFT algorithm is activated at 0.33 s
chosen for the analysis. into charging. Furthermore, simulations under different grid
2) Permanent grid disturbances higher than the resonance: impedance conditions show the effectiveness of the damping
The algorithm will detect the harmonic closer to this dis- scheme developed (see Fig. 17).
tortion and treat it as a fictitious resonance with an equiva-
lent grid impedance and a corresponding damping resistor
value. Thus, both the resonance frequency and the distor- V. EXPERIMENTAL RESULTS
tion will be attenuated. For the purpose of experimental validation, a test bench
The algorithm is repetitive during charging and adjusts online was developed at the SATIE laboratory (see Fig. 18). The
the value of the damping resistor of Fig. 13. A drawback of control is implemented using a Texas Instruments DSP with
this method is that the computational efforts increase with the TMS320F28335 microcontroller. The DSP is plugged into an in-
number of harmonic ranks to be analyzed. terface board that adapts the voltage and current sensors’ output

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 6200 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016

Fig. 17. Simulation results of the AD associated with resonance frequency

tracking activated at 0.33 s for different grid impedance values.

Fig. 20. Experimental results for ϕ ∗ = 0° before and after activation of the AD.
(a) Converter voltage. (b) Damped grid current. (c) Fundamental components of
the converter voltage and grid current displaced by 0∗ . (d) DC current resulting
from a boost hysteretic current control.
Fig. 18. Experimental test bench developed at the SATIE laboratory.

applying a displacement angle of 0° and 30°, respectively, be-

tween the fundamentals of the two signals.

B. AD Results
The damping shown in Fig. 13 is activated and its effect on
the attenuation of the input filter’s resonance is clearly shown
in Fig. 20.

C. Compliance With the IEC Standard

The international standards on harmonic current emissions
applicable to EVs in Europe are the IEC 61000-3-2 and the IEC
61000-3-12. For charging at 600 W with an RMS value of 6 A
for the grid current, the applicable IEC standard is the 61000
3-2. It defines the limits for each of the current harmonics up
Fig. 19. Experimental results for two different displacement angle references.
(a) Converter voltage. (b) Grid current showing a periodical resonance. (c) to the 40th rank. However, it does not specify limitations re-
Fundamental components of the converter voltage and grid current displaced by garding THD. Therefore, Fig. 21 introduces a comparison of
ϕ∗ . the low-frequency spectrum with the limits defined by the IEC,
before [see Fig. 21(a)] and after [see Fig. 21(b)] activation of the
levels to the DSP’s analog to digital converters’ requirements. damping. The proposed method achieves the required compli-
LEM’s LA 100-P hall-effect current sensor is used for the grid ance with the standard. The fluke 41B single-phase power qual-
current measurement and a differential voltage probe measures ity analyzer is used to study the THD levels and low-frequency
the converter’s voltage. The experimental setup’s parameters spectrum of the grid current. The THD level drops from 14%
used for charging are given in Table II. Unlike simulations, the to 8.3% upon activation of the damping and the grid current’s
grid impedance is unknown and varies from one ac power outlet distortion is highly attenuated.
to the other. The experimental results are provided for a 600-W
single-phase charger. VI. SYSTEM LIMITATIONS
Different aspects need to be taken into consideration when
A. DPFC Results
designing any PFC converter associated with AD. In fact,
In order to verify the displacement of the grid current with two design criterions must be carefully chosen: the converter’s
regards to the converter’s voltage using the DPFC scheme de- switching frequency and the filter’s resonance frequency. Usu-
scribed in Fig. 6, tests are run for two different displacement ally, the switching frequency is decided at an early stage of the
angle references. Fig. 19 shows the apparent resonance when design; then, the input filter parameters are calculated based

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 SABER et al.: CHALLENGES FACING PFC OF A SINGLE-PHASE ON-BOARD CHARGER FOR ELECTRIC VEHICLES 6201

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 6202 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016

a variable sample rate,” IEEE Trans. Power Electron., vol. 20, no. 4, Denis Labrousse was born in France, in 1981. He
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Christelle Saber (S’12) was born in Lebanon, in

1989. She received the B.Eng. and M.S. degrees
in electrical engineering from the Ecole Supérieure
des Ingénieurs de Beyrouth, Beyrouth, Lebanon, in
2012 and 2013, respectively, and also the M.S. de-
gree in mobility and electrical vehicles with honors
from ParisTech, Paris, France, in 2013. Since May
2014, she has been working toward the Ph.D. de-
gree at the French Car Manufacturer Groupe Renault,
Guyancourt, France, in collaboration with the Labo-
ratory of Systèmes et Applications des Technologies
de l’Information et de l’Energie, Cachan, France.
Her research interests include power factor correction schemes for on-board
battery chargers as well as EMC of power converters.

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