DIGITALLOGICDESIGN

Lecture 3
COURSEOUTLINE
1. Introduction
2. Gate-Level Minimization
3. Combinational Logic
4. Synchronous Sequential Logic
5. Registers and Counters
6. Memories and Programmable Logic

2
4-VARIABLEMAP
• Notice the order of the minterms

• Remember that the cells in the top row

are adjacent to the cells in the bottomrow

• Rememberthat cells in the mostleft

column are adjacent to cells in the most
right column

• Remember that cells in the four corners

are adjacent to each other

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 NOTESONA4-VARIABLEMAP
•The number of adjacent squares that may be combined must always
represent a number that is a power of two, suchas 1, 2, 4, 8 and 16
•Asmore adjacent squares are combined, we obtain a product term
with fewer literals
• One square represents one minterm, giving a term with 4 literals
• Two adjacent squares represent a term with 3 literals
• Four adjacent squares represent a term with 2 literals
• Eight adjacent squares represent a term with 1 literal
• Sixteen adjacent squares encompass the entire map and produce a
function that is always equal to logic 1
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 4-VARIABLEMAP:EXAMPLEI
Simplify the Boolean expression:
𝐹 𝐴, 𝐵, 𝐶, 𝐷 = Σ(0,1,2,4,5,7,8,9,10,12,13)

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 4-VARIABLEMAP:EXAMPLEI
Simplify the Boolean expression:
𝐹 𝐴, 𝐵, 𝐶, 𝐷 = Σ(0,1,2,4,5,7,8,9,10,12,13)

𝐹 𝐴, 𝐵, 𝐶, 𝐷 = 𝐶 ′ + 𝐵′𝐷′ + 𝐴′𝐵𝐷

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 4-VARIABLEMAP:EXAMPLEII
Simplify the Boolean expression:
𝐹 𝑤, 𝑥, 𝑦, 𝑧 = Σ(0,1,2,4,5,6,8,9,12,13,14)

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 4-VARIABLEMAP:EXAMPLEII
Simplify the Boolean expression:
𝐹 𝑤, 𝑥, 𝑦, 𝑧 = Σ(0,1,2,4,5,6,8,9,12,13,14)

𝐹 𝑤, 𝑥, 𝑦, 𝑧 = 𝑦 ′ + 𝑤 ′ 𝑧 ′ + 𝑥𝑧′

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 CHOICEOFBLOCKS
We can simplify a function by using larger blocks
🢝 Do we really need all blocks?
🢝 Can we leave some out to further simplify an expression?
Any function needs to contain a special type of blocks
🢝These are called Essential Prime Implicants
We need to define some new terms:
🢝 Implicant
🢝 Prime implicant
🢝 Essential prime implicant

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 TERMINOLOGY

Implicant (I)
🢝Any product termin the SOP form
🢝A block of 1sin a K-map
Prime implicant (PI)
🢝Block of 1s that cannot be further increased
🢝Product termthat cannot be further reduced
Essential prime implicant (EPI)
🢝A prime implicant on a K-map which covers at least one 1 which is not covered by
any other prime implicant is called an Essential Prime Implicant

Is 𝐶’ an essential prime implicant?

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THESYSTEMATICPROCEDUREFOR
SIMPLIFYING BOOLEANFUNCTIONS

1. Generate all Prime Implicants of the function

2. Include all Essential Prime Implicants
3. For the remaining mintermsnot included in the
Essential Prime Implicants, select a set of other
Prime Implicants to cover them, with minimal
overlap in the set
4. The resulting simplified function is the logical OR
of the product terms selected above

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 ILLUSTRATINGTHETERMS:EXAMPLEI
The Prime Implicants are:

1 1

1 1 1

1 1 1

1 1

• Of which only two are Essential:

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 ILLUSTRATINGTHETERMS:EXAMPLEI
The Prime Implicants are:
• 𝐴 ′ 𝐷 𝑔𝑟𝑎𝑦 ,
• 𝐴𝐶 𝑟𝑜𝑠𝑒 ,
• 𝐵𝐶 ′ 𝐷 ′ 𝑝𝑖𝑛𝑘 ,
• 𝐶𝐷 𝑝𝑢𝑟𝑝𝑙𝑒 ,
• 𝐴𝐵𝐷 ′ 𝑔𝑟𝑒𝑒𝑛 ,
• 𝐴 ′ 𝐵𝐶 ′ (𝑦𝑒𝑙𝑙𝑜𝑤).

• Of which only two are Essential:

• 𝐴 ′ 𝐷 𝑔𝑟𝑎𝑦 𝑎𝑛𝑑 𝐴𝐶 𝑟𝑜𝑠𝑒
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 ILLUSTRATINGTHETERMS:EXAMPLEII
The Prime Implicants are:

1 1 1

1 1 1

• Of which only four are Essential:

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 ILLUSTRATINGTHETERMS:EXAMPLEII
The Prime Implicants are:
• 𝐵𝐷 𝑔𝑟𝑎𝑦 ,
• 𝐴′𝐵𝐶′ 𝑦𝑒𝑙𝑙𝑜𝑤 ,
• 𝐴𝐶 ′ 𝐷 𝑝𝑢𝑟𝑝𝑙𝑒 ,
• 𝐴𝐵𝐶 𝑔𝑟𝑒𝑒𝑛 ,
• 𝐴′𝐶𝐷 𝑟𝑜𝑠𝑒 .

• Of which only four are Essential:

𝐴′ 𝐵𝐶′ 𝑦𝑒𝑙𝑙𝑜𝑤 , 𝐴𝐶′ 𝐷 𝑝𝑢𝑟𝑝𝑙𝑒 , 𝐴𝐵𝐶 𝑔𝑟𝑒𝑒𝑛
𝑎𝑛𝑑 𝐴′𝐶𝐷 𝑟𝑜𝑠𝑒 . 15
PRODUCTOFSUMS
SIMPLIFICATION USINGK-MAPS
•Use the SOP simplification on the zerosof the
function in the K-map to get 𝐹’
• Find the complement of 𝐹’, i.e. 𝐹’ ′ = 𝐹
•Recall that the complement of a Boolean function can
be obtained by (1) taking the dual and (2)
complementing each literal
• Or by using DeMorgan’stheorem

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 PRODUCTOFSUMSMINIMIZATION
How to generate a POSfrom a K-map?
•Use duality of Boolean algebra
(DeMorgan’s law)
CD
00 01 11 10
• Look at the 0s in map instead of the 1s AB

• Generate blocks around the 0s 00 1 1 0 1

🢝This gives the inverse of 𝐹
01 0 1 0 0
🢝Use duality to generate POS
11 0 0 0 0
Example:
🢝𝐹 = ∑(0,1,2,5,8,9,10)
10 1 1 0 1

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 PRODUCTOFSUMSMINIMIZATION
How to generate a POSfrom a K-map?
•Use duality of Boolean algebra
(DeMorgan’s law)
CD
00 01 11 10
• Look at the 0s in map instead of the 1s AB

• Generate blocks around the 0s 00 0

🢝This gives the inverse of 𝐹
01 0 0 0
🢝Use duality to generate POS
11 0 0 0 0
Example:
🢝𝐹 = ∑(0,1,2,5,8,9,10)
10 0

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 PRODUCTOFSUMSMINIMIZATION
How to generate a POSfrom a K-map?
•Use duality of Boolean algebra
(DeMorgan’s law)
• Look at the 0s in map instead of the 1s
• Generate blocks around the 0s
🢝This gives the inverse of 𝐹
🢝Use duality to generate POS
Example:
🢝𝐹 = ∑(0,1,2,5,8,9,10)
🢝𝐹′ = 𝐴𝐵 + 𝐶𝐷 + 𝐵𝐷 ′
🢝𝐹 = (𝐴′ + 𝐵′)(𝐶 ′ + 𝐷′)(𝐵′ + 𝐷)

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 GATEIMPLEMENTATION
SOP using: POS using:
• The 1s in the k-map • The 0s in the k-map

𝐹 = 𝐵′𝐷′ + 𝐵′𝐶′ + 𝐴′𝐶′𝐷 𝐹 = (𝐴′ + 𝐵 ′ )(𝐶 ′ + 𝐷′)(𝐵′ + 𝐷)

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 EXAMPLEONPOSMINIMIZATION
🢝Given the K-map below, produce
the 𝐹′ from the zeros in the map
and then obtain 𝐹 from it

𝐹 ′ = AB′+AC′+A′BCD ′
𝐹 = (AB′)(AC′)(A′BCD′ )
𝐹 = (𝐴′ + 𝐵)(𝐴′ + 𝐶)(𝐴 + 𝐵 ′ + 𝐶′ + 𝐷)
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 DON’TCARECONDITIONS
🢝There may be a combination of input values which:
🢝Will never occur,
🢝If they do occur, the output is of no concern

🢝The function value for such combinations is called a don’t care

🢝They are usually denoted with an 𝑋

🢝Each 𝑋 may be arbitrarily assigned the value 0 or 1 in an

implementation

🢝Don’t cares can be used to further simplify a function

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 MINIMIZATIONUSINGDON’TCARES
🢝Treat don’t cares as if they are 1s to generate Prime Implicants

🢝Delete Prime Implicants that cover only don’t care minterms

🢝Treat the covering of the remaining don’t care minterms as optional in

the selection process (i.e. they maybe, but need not be covered)

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 MINIMIZATIONEXAMPLE
𝐹 𝑤, 𝑥, 𝑦, 𝑧 = ∑(1,3,7,11,15) and 𝑑 𝑤, 𝑥, 𝑦, 𝑧 = ∑(0,2,5)
What are the possible solutions?

𝐹 = 𝑦𝑧 + 𝑤 ′ 𝑥′ 𝐹 = 𝑦𝑧 + 𝑤 ′ 𝑧 24
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EXAMPLEINVOLVINGX
Simplify the function whose K-map is shown at the
right

𝐹 = 𝐴 ′ 𝐶 ′ 𝐷 + 𝐴𝐵′ + 𝐶𝐷 ′ + 𝐴′𝐵𝐶′
or
𝐹 = 𝐴 ′ 𝐶 ′ 𝐷 + 𝐴𝐵 ′ + 𝐶𝐷 ′ + 𝐴′𝐵𝐷′

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ANOTHEREXAMPLE
Simplify the function whose K-map is shown at
the right

𝐹 = 𝐴 ′ 𝐶 ′ + 𝐴𝐵
or
𝐹 = 𝐴 ′ 𝐶 ′ + 𝐵𝐷′

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 NANDANDNORIMPLEMENTATIONS
•Digital circuits are frequently constructed with NAND or NOR gates
rather than AND & OR gates
• NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic families

A NAND gate has the smallest

propagation time delay among the
other gates, except for the inverter!

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NANDANDNORIMPLEMENTATIONS
Vdd Vdd

Gnd Gnd

• Each NAND or NOR gate requires only 4 transistors

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 A B C
0 0 1
0 1 1

NANDIMPLEMENTATION 1
1
0
1
1
0
vdd

A B 0 1

C
A

B 0 1

Gnd

• Each NAND gate requires only 4 transistors

• C = (AB)’

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 A B C
0 0 1
0 1 1

NANDIMPLEMENTATION 1
1
0
1
1
0
vdd vdd

0 0 0 1

1 vdd

0 0 1

Gnd Gnd

• Each NAND gate requires only 4 transistors

• C = (AB)’

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 A B C
0 0 1
0 1 1

NANDIMPLEMENTATION 1
1
0
1
1
0
vdd vdd

0 1 0 1

1 vdd

1 0 1

Gnd Gnd

• Each NAND gate requires only 4 transistors

• C = (AB)’

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 A B C
0 0 1
0 1 1

NANDIMPLEMENTATION 1
1
0
1
1
0
vdd vdd

1 0 0 1

1 vdd

0 0 1

Gnd Gnd

• Each NAND gate requires only 4 transistors

• C = (AB)’

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 A B C
0 0 1
0 1 1

NANDIMPLEMENTATION 1
1
0
1
1
0
vdd vdd

1 1 0 1

0 Gnd

1 0 1

Gnd Gnd

• Each NAND gate requires only 4 transistors

• C = (AB)’

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 A B C
0 0 1
0 1 0

NORIMPLEMENTATION 1
1
0
1
0
0
vdd

A
0 1

A B

0 1

Gnd

• Each NOR gate requires only 4 transistors

• C = (A+B)’

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 A B C
0 0 0
0 1 0

ANDNAND-BASEDIMPLEMENTATION 1
1
0
1
0
1
vdd

A B 0 1

C C’

B 0 1

Gnd Gnd

• Each AND gate requires 6 transistors

• C = AB

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 A B C
0 0 0
0 1 0

ANDNAND-BASEDIMPLEMENTATION 1
1
0
1
0
1
vdd

A B 0 1

C=0 C’=1
vdd
A

B 0 1

Gnd Gnd

• Each AND gate requires 6 transistors

• C = AB

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 A B C
0 0 0
0 1 0

ANDNAND-BASEDIMPLEMENTATION 1
1
0
1
0
1
vdd

A B 0 1

C=1 C’=0
Gnd
A

B 0 1

Gnd Gnd

• Each AND gate requires 6 transistors

• C = AB

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 LOGICOPERATIONWITHNANDGATE
NOT, AND, and OR can be implemented with NAND!

The complement
operation is obtained
from a one-input NAND
gate that behaves
exactly like an inverter

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CONVERSIONTONANDIMPLEMENTATION
Minimized expressions are AND-OR combinations
🢝There are two illustrations for NAND gates

Key observation: two “bubbles” eliminate each other

Two bubbles equal a straight wire
How to generate a sum of minterms using NAND?
🢝Use AND-invert for minterms
🢝Use invert-OR for sum
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 NAND
Representations

CONVERSIONTONAND
IMPLEMENTATION
• Sum of minterms

• Replace AND with AND-invert and

A
OR with invert-OR B
🢝Still the same circuit!
C
D
•Replace AND-invert and invert-OR
with NAND A
🢝𝐹 = (𝐴𝐵)′(𝐶𝐷)′ = 𝐴𝐵 + 𝐶𝐷 B

C
D
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 NAND
Representations

CONVERSIONTONAND
IMPLEMENTATION
• Sum of minterms

• Replace AND with AND-invert and

OR with invert-OR
🢝Still the same circuit!

•Replace AND-invert and invert-OR

with NAND
🢝𝐹 = (𝐴𝐵)′(𝐶𝐷)′ = 𝐴𝐵 + 𝐶𝐷

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 NAND
Representations

NANDEXAMPLE
IMPLEMENTATION
Minimize and implement the
function
𝐹(𝑥, 𝑦, 𝑧) = ∑(1,2,3,4,5,7),
𝐹 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦 + 𝑧
using only NAND gates

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 MULTILEVELNANDCIRCUITS
Multilevel circuits conversion rules:
1. Convert all AND gates to NAND with AND-invert symbols
2. Convert all OR gates to NAND with invert-OR symbols
3. Check all bubbles in the diagram. For every bubble that is not
compensated by another bubble, insert an inverter.
Example:

43
 NAND
Representations

MULTILEVEL
NAND CIRCUITS
Multilevel circuits conversion rules:
1. Convert all AND gates to NAND with AND-invert symbols
2. Convert all OR gates to NAND with invert-OR symbols
3. Check all bubbles in the diagram. For every bubble that is not
compensated by another bubble, insert an inverter.
Example:

44
 NAND
Representations

MULTILEVEL
NAND CIRCUITS
Multilevel circuits conversion rules:
1. Convert all AND gates to NAND with AND-invert symbols
2. Convert all OR gates to NAND with invert-OR symbols
3. Check all bubbles in the diagram. For every bubble that is not
compensated by another bubble, insert an inverter.
Example:
𝑪𝑫 𝑪𝑫

𝑩 𝑩
𝑨 𝑨
𝑩𝑪 𝑩𝑪

45
 NAND
Representations

MULTILEVEL
NAND CIRCUITS
Multilevel circuits conversion rules:
1. Convert all AND gates to NAND with AND-invert symbols
2. Convert all OR gates to NAND with invert-OR symbols
3. Check all bubbles in the diagram. For every bubble that is not
compensated by another bubble, insert an inverter.
Example:

𝑩 + 𝑪𝑫 𝑩 + 𝑪𝑫

𝑨 𝑨
𝑩𝑪 𝑩𝑪

46
 NAND
Representations

MULTILEVEL
NAND CIRCUITS
Multilevel circuits conversion rules:
1. Convert all AND gates to NAND with AND-invert symbols
2. Convert all OR gates to NAND with invert-OR symbols
3. Check all bubbles in the diagram. For every bubble that is not
compensated by another bubble, insert an inverter.
Example:

𝑩 + 𝑪𝑫 𝑨 (𝑩 + 𝑪𝑫)𝑨

𝑩𝑪 𝑩𝑪

47
 NAND
Representations

MULTILEVELNAND
CIRCUITS:ANEXAMPLE
𝐹 = (𝐴𝐵′ + 𝐴′𝐵)(𝐶 + 𝐷′)

48
 NAND
Representations

MULTILEVELNAND
CIRCUITS:ANEXAMPLE
𝐹 = (𝐴𝐵′ + 𝐴′𝐵)(𝐶 + 𝐷′)

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 NAND
Representations

MULTILEVELNAND
CIRCUITS:ANEXAMPLE
𝐹 = (𝐴𝐵′ + 𝐴′𝐵)(𝐶 + 𝐷′)

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 NAND
Representations

MULTILEVELNAND
CIRCUITS:ANEXAMPLE
𝐹 = (𝐴𝐵′ + 𝐴′𝐵)(𝐶 + 𝐷′)

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 LOGICOPERATIONWITHNORGATE
NORcan also replace NOT, AND & OR

The complement
operation is obtained
from a one-input NOR
gate that behaves
exactly like an inverter

There are two representations of the NORgate:

52
 NOR
Representations

CONVERTINGTONOR
IMPLEMENTATIONS
Same rulesas for NAND implementations
𝐹 = (𝐴𝐵′ + 𝐴′𝐵)(𝐶 + 𝐷′)

With NOR
𝐹 = (𝐴𝐵′ + 𝐴′𝐵)(𝐶 + 𝐷′)

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