See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/286439699

Design and Analysis of CNTFET-Based SRAM

Article · July 2015

CITATIONS READS

16 5,645

2 authors, including:

Arvind R. Singh
Hanjiang Normal University
116 PUBLICATIONS 3,686 CITATIONS

SEE PROFILE

All content following this page was uploaded by Arvind R. Singh on 10 December 2015.

The user has requested enhancement of the downloaded file.

 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 02 Issue: 04 | July-2015 www.irjet.net p-ISSN: 2395-0072

Design and Analysis of CNTFET-Based SRAM

Monish Jaiswal1, Arvind R. Singh2
1 Assistant Professor, Electronics Engineering Department, RGCER Nagpur (M.S.), India
2 Assistant Professor, Electrical Engineering Department, MMCOE Pune (M.S.), India

---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - Carbon Nano Tube Field Effect Transistors consumption. In this regard SRAM Cell design using
(CNTFETs) are being widely studied as possible CNTFET proves useful as CNTFET require less threshold
successors to silicon MOSFETs. In a CNTFET, the threshold voltage. SRAM cell performances are usually measured in
voltage can be adjusted by controlling the chirality vector terms of static noise margin and write time.
(i.e. the diameter). Therefore Design of SRAM Cell based Implementations of SRAM cell with different chirality for
on CNTFET is important for Low-power cache memory. In n- and p-CNTFET are made.
this paper we have successfully developed a compact
model for MOSFET like CNTFET. This paper begins with 2. CARBON NANO TUBE FIELD EFFECT TRANSIST-
the analysis of the CNTFET. The dependency of I-V ORS
characteristics on chirality is studied and then 6-T based CNT is a tubular form of carbon with diameter as small as
SRAM is designed with different chirality for n-CNTFET 1nm. The length of the tube ranges from a few nm to µm. A
AND p-CNTFET. The performance of the SRAM cell is CNT is characterized by its Chiral Vector: Ch = n â1 + m â2,
measured In terms of write time for high speed and static   Chiral Angle with respect to the zigzag axis ,
noise margin for stability of the cell.

Key Words: CNT, CNTFET, SRAM, Chirality, Write Time,

SNM

1. INTRODUCTION
The increasing demand of more and more functionality
on-chip with the fastest ever-possible speed at the cost of
minimum power consumption is putting a question mark
on the existing semiconductor technology. For few
decades the scalability of the S.C. technology has solved
the problems to some extent, but soon it will reach its limit
due to quantum mechanical effect. The existing S.C.
technology has also put limit on the speed with
substantially more power consumption due to increase in
the number of devices; causing more inter-connect delays
and more static power consumption. Thus it is allowing
speed up to a few GHz only with the limit on operation of
minimum threshold for the chip. This focuses attention on Fig. 1 Graphene sheet rolling up to CNT
search of alternatives that can replace or integrate with where â1 and â2 are lattice basis vectors of graphene sheet
silicon in nano-scaled transistors to resolve the existing and the chiral angle represents the angle that the axis of
problems and meet the today’s requirement. The carbon rolling up sheet forms with one of the basis vectors. On the
nanotube is one among the most promising alternatives basis of chirality CNT can be classified as, zig zag ( = 0),
due to its superior electrical properties. The use of carbon Chiral (0 < < 30), or armchair (with  = 30).
nanotube with silicon technology not only causes A single-wall carbon nanotube (or SWCNT) consists of
reduction in threshold voltage but also allows the speed to only one cylinder, and the simple manufacturing process
reach in THz or PHz. of this device makes it a very promising alternative to
today’s MOSFET. An SWCNT can act as either a conductor
This exceptional behaviour of carbon nanotube has been or a semiconductor depending on the angle of the atom
utilised in the design of CNTFET and proved to be boon as
arrangement along the tube. This is referred to as the
static power consumption gets reduced considerably. Now
chirality vector and is represented by the integer pair (n,
the research is going on the design of memory subsystem m). A simple method to determine if a carbon nanotube is
which is a major part of any electronic system requires
metallic or semiconducting is based on considering the
higher speed with low power consumption. Static Random
indices (n, m), i.e. the nanotube is metallic if n=m or n-
Access Memories (SRAMs), being a crucial component in m=3i where i is an integer. Otherwise, the tube is
the memory hierarchy of modern computing systems,
needs to be very-fast accessible with low power
© 2015, IRJET.NET- All Rights Reserved Page 11
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 02 Issue: 04 | July-2015 www.irjet.net p-ISSN: 2395-0072

semiconducting. The diameter of the CNT with chirality (n,

m) can be calculated as
DCNT= (a0)/π *(n2+nm+m2)1/2

Fig -2: CNTFET Structure Fig -4: Id vs. Vgs plot for n-CNTFET
Carbon nanotube field effect transistors (CNTFETs) utilize
semiconducting single-wall CNTs to assemble electronic
devices; CNTFETs are having similar properties to
MOSFETs. The CNTFET device current is saturated at
higher Vds (drain to source voltage) as channel length
increases as shown in Fig.3, and the on-current decreases
due to energy quantization in the axial direction at 32-nm
(or less) gate length. The threshold voltage is defined as
the minimum gate-source voltage required to turn on the
transistor, and the threshold voltage of the CNT channel
can be defined as the half band-gap which is an inverse
function of the diameter
Vth =Eg/2e= ((3)1/2/3)*(a0.V/eDCNT)

where ‘a0’ = 2.49 Å is the carbon-to-carbon atom distance, Fig -5: Id vs. Vds plot for n-CNTFET
‘V’ = 3.033 eV is the carbon π-π bond energy in the tight Owing to high Ion/Ioff ratio, CNTFET can have better scope
bonding model, ‘e’ is the unit electron charge, and ‘DCNT’ is as a switch. The inverter can be formed by combination of
the diameter of CNT. Thus the threshold voltage of the p-CNTFET and n-CNTFET (as shown in Fig.6). The output
CNTFET will change with the chiral indices. The threshold voltage has very less delay in transition from one state to
voltage of the CNTFET is inversely proportional to the other acting as almost ideal switch.(fig.).The voltage
chirality vector of the CNT (as shown in fig.4). The transfer characteristic of the inverter reveals that it has
saturation current is also found to be function of chiral very high noise margin.
index, which means that on-off current ratio is very high
for CNTFET.

Fig -3: Circuit Schematic for I-V Characteristic of N-

CNTFET Fig -6: Circuit Schematic for CNTFET-Based Inverter

© 2015, IRJET.NET- All Rights Reserved Page 12

 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 02 Issue: 04 | July-2015 www.irjet.net p-ISSN: 2395-0072

Fig -7: CNTFET-Based Inverter Logic Verification

Fig -9: CNTFET-based Inverter Voltage Transfer
3. SRAM CELL DESIGN Characteristics
Two cross coupled inverters along with two switches The 6-transistor SRAM model is shown here. The proper
forms a simple SRAM cell. The coupled inverter stores the sizings of the transistors are required in order to maintain
bit at the two nodes, q & q_bar, and the switch act as the its state while reading and holding the stored value. For
switch for reading and writing of the data. reading operation to perform, the size of n-CNTFET used
in cross-coupled inverter (N1& N3) should be greater than
that of pass-transistor (N2&N4). The performance of
SRAM cell is measured in terms of stability and the write
time. The write time is defined as the time required to
write the bit inside the cell. The write time is measured as
the time interval when 50% of the time when the data
input is changing to the 50% of the time when data is
stored in the SRAM cell. Static Noise Margin is defined as
the maximum level of dc perturbance that a cell node can
tolerate before changing its state. Static noise is dc
disturbance such as offsets and mismatches due to
processing and variations in operating conditions.
Fig -8: Basic SRAM Cell
The switches are usually designed using NMOS pass
transistors with wordline as enable input. The low
wordline implies disconnection of the cyclic inverter with
bitline and the internal state of the coupled inverter will
be preserved. The SRAM cell structure shown above is
fully symmetric. and READ and WRITE operations are
performed using both bitlines, BL and BL ’ While reading or
writing, common wordline (i.e., WL) controls accessibility
to the cell nodes q and q_bar through two pass transistor.

SRAM cells are used to implement high capacity memories

that require low power consumption, short access times,
and high endurance to process variations and
environmental conditions. Writing operation of SRAM cell
can be performed by loading the bitlines BL and BL ’ with
the new value and its complement using write circuit
Fig -10: 6-transistors based SRAM cell
respectively and raising wordline high simultaneously.
READing data out of the cell is performed by first 4. IMPLEMENTATION AND RESULTS
precharging both the bitlines high and then reading the The model of CNTFET are made using Verilog-A code as
data through the when the wordline is raised turning on per given by Stanford University. Using that code, symbols
the pass transistors. for p- and n-CNTFET are created in CADENCE-Virtuoso.
The 6-T SRAM cell for write operation with proper
chirality is designed in 32-nm Technology. The sizing of
© 2015, IRJET.NET- All Rights Reserved Page 13
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 02 Issue: 04 | July-2015 www.irjet.net p-ISSN: 2395-0072

transistors i.e., the no. of tubes for N1&N2 CNTFET are 5 found to be 365.2mV and 412.5mV for p-CNTFET chiral
and 4 respectively, while p-CNTFET has 3tubes. The indices of (16, 0) and (19, 0) respectively.
channel length is set to be 32 nm, and the chiral vectors
for N1 &N2 transistors are (19, 0). The chiral index of p-
CNTFET are taken as (19,0) and (16,0) for two
simulations.

Fig -13: CNTFET-based SRAM cell for SNM calculation

Fig -11: CNTFET-based SRAM cell for WRITE Operation

The write operation is performed by suppling data_in to
bitlines. For data_in=111100001111, the waveforms of q
and q_bar are plotted in the fig. The write time for p-
CNTFET chiral indices of (19, 0) and (16, 0) are calculated
and found to be as 2.71 ps and 2.04 ps respectively.

Fig -14: Cell data transitions due to two series voltage

noise sources

5. CONCLUSIONS
The 6T-SRAM cell was designed using CNTFETs with
different chiral indices. The dependency of I-V
characteristics on chirality was studied and then 6-T based
SRAM was designed with different chirality for n-CNTFET
Fig -12: CNTFET-based SRAM cell write timing diagram AND p-CNTFET. The performance of the SRAM cell was
for data_in=111100001111 measured In terms of write time for high speed and static
noise margin for stability. SRAM cell with 4 n-CNTFET of
For read operation the bitlines are precharged to Vdd and chirality(19,0) and 2 p-CNTFET of (16,0) had low write
capacitors are connected to the bitline to allow time and high SNM, it can be used for high speed SRAM
discharging it the corresponding node is storing 0 value. design with high stability. The write time for this cell was
The static noise margin is calculated by modelling internal coming to be 2.04 ps. And static noise margin was found to
noise as Vn voltage source and then varying this value be 365.2mV. 6T SRAM cell designing method was proved
to be more accurate and highly stable due to static noise
from Vn=0 V to Vn=Vdd/2. The state voltage q and q_bar
reduction.
are plotted against Vn (fig.). The static noise margin are

© 2015, IRJET.NET- All Rights Reserved Page 14

 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 02 Issue: 04 | July-2015 www.irjet.net p-ISSN: 2395-0072

REFERENCES BIOGRAPHIES
[1] A. Akturk, G. Pennington, N. Goldsman, “A. Monish Jaiswal completed his
Wickenden, Electron Transport and Velocity M.Tech from Government College
Oscillations in a Carbon Nanotube,” IEEE Trans. of Engineering Amravati. Working
Nanotechnol., Volume 6, Issue 4, pp 469 – 474, July as an Assistant Professor in
2007J.
Electronics Engineering Depar-
[2] Y. Lin, J. Appenzeller, J. Knoch, P. Avouris, “High-
performance carbon nanotube field-effect transistor tment, RGCER Nagpur. Research
with tunable polarities,” IEEE Trans. Nanotechnol., interests are in VLSI Design,
Vol 4, Issue 5, pp 481 - 489, Sept. 2005. Embedded system Design, and
[3] S. Lin, Y.B. Kim, F. Lombardi, and Y.J. Lee, “A New Signal Processing.
SRAM Cell Design Using CNTFETs,” in Proceedings of Arvind R. Singh completed his
IEEE International SoC Conference 2008, pp. 168 - M.Tech from College of Engin-
171, Nov. 2008 eering Pune. Working as an
[4] Murotiya, S.L.., Gupta A., “CNTFET based design of Assistant Professor in Elect-rical
Content addressable Memory Cells”, in IEEE Department at MMCOE, Pune.
Conference Sept 2013, pp. 1-4.
Research interests are in power
[5] A. Pushkarna; S. Raghavan; “Comparison of
performance parameters of SRAM designs in 16nm system, VLSI Design, and Signal
CMOS and CNTFET technologies”, in IEEE Conference, Processing.
27-29 Sept. 2010
[6] Arvind R.Singh; K.Venkata Rama Mohan, Santhosh
Kompelli;“Advance Distance Protection Of Trans-
mission Line In Presence of Shunt Compensator”, in
IRJET 2015, Vol.1, Issue 3.
[7] Sheng Lin; Yong-Bin Kim; Lombardi, Fabrizio;
“Design of a Ternary Memory Cell Using CNTFETs”, in
IEEE Transactions, 2012, Vol.11, Issue:5.
[8] Srinivasan, P.; Bhat, A.S.; Murotiya, S.L.; Gupta, A.;
“Design and performance evaluation of a low
transistor ternary CNTFET SRAM cell”, in IEEE
Conference, 2015, pp. 38-43

© 2015, IRJET.NET- All Rights Reserved Page 15

View publication stats