DENSITY CHECKS

-CVN REDDY SEELM

1. Introduction to Density Checks

In modern VLSI design and fabrication, density checks play a critical role in ensuring

that the integrated circuit (IC) layout adheres to uniformity constraints, both locally and

globally. Density rules are verified during the physical verification stage to avoid

manufacturing problems caused by uneven material deposition or removal during

fabrication processes such as chemical-mechanical polishing (CMP), etching, and

deposition

2. Why Density is Important in Fabrication

Fabrication is a highly precise and sensitive process. Semiconductor wafers go through

a variety of steps such as etching, ion implantation, and planarization. These processes

are susceptible to layout density variations:

2.1 Chemical Mechanical Polishing (CMP) Issues

CMP is used to flatten layers during the fabrication process. If certain areas of the chip

have too much metal (high density) while others have very little (low density), it leads

to:

• Over-polishing (erosion) in high-density regions

• Under-polishing (dishing) in low-density regions

These defects can result in:

• Non-uniform topography

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 • Poor metal coverage

• Open or short circuits

• Yield loss and device failure

2.2 Etching and Deposition Uniformity

Density impacts how etching and deposition work:

• Dense regions might not etch completely

• Sparse regions may face over-etching or under-deposition

• Maintaining a balance ensures process uniformity and reliable pattern transfer

onto silicon wafers.

3. Types of Density Rules

Density checks can be categorized as:

3.1 Global Density Rules

These ensure the entire chip maintains a specific average metal density (e.g., 30%–70%)

to meet process uniformity.

3.2 Local Density Rules

These focus on smaller areas like a 100µm × 100µm window, ensuring density variations

are within limits, especially critical for localized CMP effects.

3.3 Edge and Corner Density

Special rules to manage density near die edges and corners due to etching and polishing

non-uniformity at boundaries.

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4. Layout Design Strategies to Handle Density

Designers need to adopt smart layout techniques to meet density requirements:

4.1 Use of Dummy Fill Structures

Dummy or "fill" patterns are added in regions with lower metal density to bring it within

acceptable limits. These do not serve electrical functions but help in process uniformity.

4.2 Smart Placement and Routing

• Distribute logic gates uniformly

• Avoid clustering too many interconnects in one region

• Ensure power grid and routing structures contribute positively to density balance

4.3 Density-aware Floorplanning

Even during chip floorplanning, care is taken to distribute functional blocks evenly

across the die to maintain uniform metal usage.

5. What are Fill Decks?

A Fill Deck is a specially designed script or rule file used in physical verification tools

(like Calibre, ICV, Pegasus) to add dummy metal structures (fills) automatically during

sign-off or pre-tapeout stages.

5.1 Purpose of Fill Decks

• Ensure local and global metal density compliance

• Automate dummy fill insertion

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 • Maintain electrical isolation (fill must not create shorts)

• Optimize performance and yield

5.2 How They Work

Fill decks use layout pattern analysis to detect low-density areas and then insert dummy

fill patterns (e.g., metal rectangles, poly fills) based on:

• Minimum spacing from active nets

• Maximum fill size allowed

• Layer-specific density targets

• Some tools also allow fill exclusion zones to prevent fill insertion in sensitive

areas (e.g., analog blocks).

6. Physical Verification: Density Rule Checks

After fill insertion, Density Rule Check (DRC) is performed as part of the Physical

Verification stage. The rule deck will:

• Slide a checking window (e.g., 100µm × 100µm) across the entire chip

• Calculate metal coverage in each window

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 • Compare it with min/max allowable density thresholds

• Flag violations if any window exceeds limits

• Tools like Calibre or ICV report these violations along with coordinates and

suggest modifications.

7. Examples and Illustration

Example 1: Metal Density Problem

A layout contains a large logic block with dense interconnects and an adjacent empty

space reserved for I/O pads. The empty region causes local density failure. To fix this:

• Fill deck inserts dummy metal rectangles in the empty region.

• These fills help maintain density between 30%–70%.

Example 2: Fill-Induced Parasitics

Although fills are electrically inactive, they may introduce unintended parasitic

capacitance. Tools optimize fill spacing from signal nets to reduce such side effects.

8. Conclusion

Density checks are fundamental to bridging the design and manufacturing divide. They

ensure process reliability and yield by balancing metal coverage across the die. Layout

designers and physical verification engineers must collaborate to:

• Understand density requirements

• Use fill decks wisely

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 • Achieve design goals without compromising manufacturability

By proactively addressing density issues during layout design, teams can significantly

reduce fabrication defects and increase chip yield and performance.

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Thank You
The VLSI Voyager
-C.V.N Reddy Seelam