The AVR Microcontroller

Presented by
Mary Nsabagwa , [email protected]
 Outline
•What is AVR Microcontroller ?
•Microprocessor Vs Microcontroller
•Memory organisation
•Microcontroller Structure
•Fuse Bits
•Timers
•Interrupts
 What is AVR?
• AVR is a family of microcontrollers developed
since 1996 by Atmel
• Acquired by Microchip Technology in 2016
• Applications:-
• Used in different types of embedded systems.
• Used in electronic devices,
• Used in industries for the control of different machines
Microprocessors Vs
Microcontrollers
•The microprocessor is a processor on one
silicon chip
•The microcontroller is a microprocessor
with added circuitry

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Microcontrollers
• Embedded Systems
• Operations managed behind the scenes by a
microcontroller
• Microcontroller (MCU)
• Integrated electronic computing device that
includes three major components on a single chip
• Microprocessor (MPU)
• Memory
• I/O (Input/Output) ports

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The AVR Microcontroller Physical
Structure
Microcontrollers

•Support Devices
•Timers
•A/D converter
•Serial I/O
•Common communication lines
•System Bus

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Input/Output (I/O)
•Input Devices
•Switches and Keypads
•Provide binary information to the
MPU
•Output devices
•LEDs and LCDs
•Receive binary information from the
MPU
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 Microprocessor Architecture
• MPU communicates with Memory and I/O using
the System Bus
• Address bus
• Memory and I/O Addresses
• Data bus
• Transfers Binary Data and Instructions
• Control lines
• Read and Write timing signals

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Software
• Machine Language
• Binary Instructions
• Difficult to decipher and write
• Error-prone
• All programs converted into machine language
for execution
Instruction Hex Mnemonic Description Processor
10000000 80 ADD B Add reg B to Acc Intel 8085
00101000 28 ADD A, R0 Add Reg R0 to Acc Intel 8051
00011011 1B ABA Add Acc A and B Motorola 6811
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 Software
• Assembly Language
• Machine instructions represented in mnemonics
• One-to-one correspondence
• Efficient execution and use of memory
• Machine-specific

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Software
• High-Level Languages
• BASIC, C, and C++
• Written in statements of spoken languages
• Machine independent
• Easy to write and troubleshoot
• Larger memory and less efficient execution

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 MPU-Based Systems

•System hardware
•Discrete components
•Microprocessor, Memory, and I/O
•Components connected by buses
•Address, Data, and Control
•System software
•Group of programs that monitors the
functions of the entire system
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Basic Features of a typical AVR microcontroller

ATmega8 - RISC Architecture

● 130 Instructions – Most Single-clock Cycle Execution

● 32 x 8 General Purpose Working Registers
● 64 x 8 Special Function Registers (I/O Registers)
● Up to 16 MIPS Throughput at 16 MHz
● On-chip 2-cycle Multiplier

Nonvolatile Program and Data Memories

● 8K Bytes of In-System Self-Programmable Flash

10,000 Write/Erase Cycles
● Optional Boot Code Section with Independent Lock Bits
● 512 Bytes EEPROM (100,000 Write/Erase Cycles)
● 1K Byte Internal SRAM
● Programming Lock for Software Security
 Basic Features
II: Atmega8 – Basic features

Peripheral Features

● Two 8-bit Timer/Counters

● One 16-bit Timer/Counter with Capture Mode
● Real Time Counter with Separate Oscillator
● Three PWM Channels
● 6-channel ADC with 10 resp 8 Bit resolution
● Two-wire Serial Interface (TWI)
● Programmable Serial USART
● Master/Slave SPI Serial Interface
● Programmable Watchdog Timer with On-chip Oscillator
● On-chip Analog Comparator
 Basic features
Special Microcontroller Features

● Internal Calibrated RC Oscillator

● External and Internal Interrupt Sources
● Five Sleep Modes

I/O and Packages

● 23 Programmable I/O Lines

● 28-lead PDIP, 32-lead TQFP, and 32-pad MLF
II: Atmega8 – Basic features
Operating Voltages

● 2.7 - 5.5V (ATmega8L)

● 4.5 - 5.5V (ATmega8)

Speed Grades

● 0 - 8 MHz (ATmega8L)
● 0 - 16 MHz (ATmega8)

Power Consumption at 4 Mhz, 3V, 25°C

● Active: 3.6 mA
● Idle Mode: 1.0 mA
● Power-down Mode: 0.5 μA
ATmega8 Pinout and Packages (PDIP and TQFP)
Mega8 CPU Core

● Seperate Instruction and

Data Memories (Harvard)

● all 32 General Purpose

Registers connected to
ALU

● I/O Modules connected to

Data Bus and accessible via
Special Function Registers
 Atmega8 – Pin and Port Overview:

GND: Ground (0V)

VCC: Digital Supply Voltage (2,7 – 5,5V)
AVCC: Analog Supply Voltage
AREF: Analog Reference Voltage, usually AVCC
/Reset: Low level on this pin will generate a reset

Port B, Port C, Port D:

General Purpose 8 Bit bidirectional I/O - Ports,
optional internal pullup-resistors when configured as input
output source capability: 20mA

Special Functions of the Ports available as configured using the Special Function
Registers (SFRs):

Port D: UART, external Interrupts, Analog Comparator

Port B: External Oscillator/Crystal, SPI
Port C: A/D converters, TWI
II: Atmega8 – Basic features

Memory organization
Atmega8 – AVR Memory organization

● Program Flash Memory:

On-chip, in system programmable

8 Kbytes, organized in 4K 16 bit words

Program Counter (PC) = 12 bits

Accessible via special instructions:

Load Program Memory (LPM)
Self Programing Mode (SPM)

Boot Loader support: Boot Flash Section,

SPM can be executed only from Boot Flash
Bootloader
• AVR flash memory is divided into two sections
• The application section
• The Boot-Loader section (BLS)
• Bootloader is a code which executes when
a microcontroller is powered ON or reset
• Sets an environment for the application code to execute
• Loads the application code from any storage medium or
received through external communication and let the
application to execute
• Written to the BLS section of the flash memory
• Has complete access to the hardware of the microcontroller.
AVR ISP Programmer
Required to download firmware to chip if there is no bootloader
AVR Memory organization
● EEPROM - Memory:

512 Bytes, single Bytes can be read and written

Special EEPROM read and write procedure using SFRs:

EEPROM Address Register, EEPROM Data Register,

EEPROM Control Register
C – Library Functions available

Precautions to prevent EEPROM memory corruption:

● no flash memory or interrupt operations

● stable power supply
 Atmega8 – Basic features

AVR Memory organization

● SRAM Data Memory:

32 GPR’s and
64 SFR’s mapped
to SRAM memory space

SFR’s accessed
via in / out instructions
(I/O-registers)

1 Kbytes of internal
SRAM can be accessed
from address 0x060
to address 0x45f

5 Direct and indirect addressing modes

Important I/O Registers:
SREG – Status Register

C Carry flag. This is a borrow flag on subtracts.

Z Zero flag. Set to 1 when an arithmetic result is zero.
N Negative flag. Set to a copy of the most significant bit of an arithmetic result
V Overflow flag. Set in case of two's complement overflow.
S Sign flag shows the true sign of a comparison
H Half carry. This is an internal carry from additions and is used to
support BCD arithmetic
T Bit copy. Special bit load and bit store instructions use this bit.
I Interrupt flag. Set when interrupts are enabled
Important I/O Registers:
Stack Pointer (SPH and SPL)

● Stack is a LIFO buffer located in SRAM

● Stack Pointer addresses the current location
● Push and pop instructions write / read from Stack
● Enter or return from subroutines / interrupt routines:
Address and Parameters transferred via Stack
Clock Options
System Clock Options:
System Clock Options:

● Clock Muliplexer selects the clock

source according to FUSE settings

● Clock Control Unit distributes clocks

clocks can be halted to reduce power consumption

● CPU Clock: CPU, ALU, GPRs

● I/O Clock: Ports, Timers, SPI, UART

● ADC Clock: seperate clock for ADC noise reduction in sleep mode

● Asynchronous Timer Clock:

external 32kHz Crystal for realtime clock, keeps timer module running
during sleep mode
AVR Fuses and Lock Bits

• Fuses are the locations in non-volatile memory that

define the hardware configuration of an AVR device
including
• Clocking

• 19 fuse bits are used in the ATmega328P in 3

different fuse bytes
• 3 fuse bits in the Extended Fuse Byte
• 8 in the Fuse High Byte
• 8 in the Fuse Low Byte
 Extended Fuse Bits

• Deals with the Brownout detection level

• Brownout detection allows a microcontroller to
reset when the supply voltage falls below a certain
level
• E.g in ATmega328P, (nominally 1.8V, 2.7V, or
4.3V) may be selected as the minimum allowable
supply voltage
• To program a fuse bit, set it low, i.e., 0 (zero)
• 1 means bit is unprogrammed
BODLEVEL: When programmed (0) the trigger level is 4V and when not programmed (1)
the trigger level is 2.7V
 Fuse High Byte
• Bits 2-0 are used to set the boot size for the ATmega328P
• Amount of memory reserved for the installation of a Boot
Loader
• RSTDISBL (external reset disable) bit 7
• SPIEN (Serial Peripheral Interface Enable) bit. Disabling
either one is often the cause for "bricked" Atmel µCs;
"leave them alone" is good advice.
• Bricking is making your MPU unrecoverable, unable to be
modified, or connected to with a debug adapter
D
 Fuse Low Byte Options
• Selects the clock source for the ATmega328P, and
controls some of the details of the clock operation
• Bit 7 controls whether or not the clock rate divide-by-8 feature is
enabled
• Bit 6 determines whether or not a clock output is present on
PORTB0 of the microcontroller
• Bits 5 and 4 control the start-up time of the microcontroller,
which is intended to prevent the chip from attempting to start
before the supply voltage has had time to reach an acceptable
minimum level
• Bits 3 through 0 are used to select the clock source
Fuse Low Byte
Clock Options
I/O Ports, Timers and
Interrupts
I/O Ports

● General Purpose IO : Data Direction Input or Output

● Internal Pullup can be used for Input Pins
● Output driver can source 20mA current
● Protection diodes to GND and VCC
I/O Ports

● 3 I/O-Registers for each port:

Data Register (r/w):

PORTB, PORTC, PORTD

Data Direction Register (r/w):

DDRB, DDRC, DDRD

Port Input Pin Register (r):

PINB, PINC, PIND

The Bits of these registers set the configuration for one Port Pin.
I/O Ports – Configuration and usage

C-Example 1 - Configure Pin B3 as output, set output level to VCC:

DDRB |= (1<<3); PORTB |= (1<<3);

C-Example 2 - Configure Pin D2 as input with pullup, read pin value:

DDRD &= ~(1<<2); PORTD |= (1<<2); uint8_t x = PIND & (1<<2);

Alternate Port functions Port B
Alternate Port functions Port C
II: Atmega8 – Basic features

Alternate Port functions Port D

 II: Atmega8 – Basic features

Interrupt Handling
• Interrupts can stop the main program from
executing to perform a separate interrupt service
routine (ISR).
• When the ISR is completed, program control is
returned to the main program at the instruction that
was interrupted
Interrupt Processing
● Several Interrupt Sources: External Interrupts, Timer, Bus-Peripherals,
ADC, EEPROM

●Individual Interrupt-Enable bits in the SFR‘s

● Global interrupt enable Bit in SREG, set with sei() and clear with cli() instruction

● Flagged (remembered) and non-flagged interrupt sources

● Lowest addresses in program memory reserved for the interrupt vector table

● Higher priority interrupts have lower addresses

 Requirements for Execution of Interrupt
Subroutine
• Interrupt source must be activated by setting the
corresponding Interrupt Mask/Interrupt Enable Bit
• The Interrupt sub routine (codes to be executed) must exist
• The Interrupt Enable flag bit in the AVR Status register
(SREG) must be set (=1)
• Instruction named ‘sei’ (Set Interrupt Enable)- Enables
the Execution of interrupt sub routine
• Finally the event must occur, so that the execution of the
routine gets triggered
II: Atmega8 – Basic features
Reset-Vector and Interrupt-Vectors

● Word addresses
0, 1 – 19 in Flash

● When a reset or
interrupt occurs,
the CPU calls
the address

● Install an Interrupt
Handler: modify
the vector table to
jump to your user-
handler

● return from interrupt:

reti
 Reset- and Interrupt- Vectors

● Reset vector can be set to the Bootloader section using the

BOOTRST fuse bit

● Interrupt vectors can be set to the Bootloader

section using the IVSEL bit of the General Interrupt Contol Register
 Reset Sources

• Power-on Reset: supply voltage is below the Power-on Reset threshold

• External Reset: low level is present on /RESET – input pin

• Watchdog Reset: Watchdog Timer enabled and period expires

• Brown-out Reset: Brown-out Detector enabled and supply voltage below

threshold

MCU Control and Status Register (MCUCSR) provides information on which reset
source caused a CPU reset
II: Atmega8 – Basic features

External Interrupts Int0 and Int1:

• Int0 connected to PD2

• Int1 connected to PD3
• asynchronous operation: can wake up CPU
• rising/falling edge or low level can trigger interrupt,
defined by Interrupt Sense control – bits of MCUCR SFU
External Interrupts Int0 and Int1:

• Int0 and Int1 have to be enabled by the GICR (+ I-bit in SREG)

• flagged interrupts: General Interrupt Flag Register (GIFR)

indicates when an interrupt request happened

• flags are cleared by executing the interrupt service routine (ISR)

or by writing 1 to the flag bit of GIFR
Bit 7 - INTF1: External Interrupt Flag 1
When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt
flag, INTF1, becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT1 in GICR are set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed or by writing a logical one to it.
This flag is always cleared when INT1 is configured as a level interrupt.
Bit 6 - INTF0: External Interrupt Flag 0
When an event on the INT0 pin triggers an interrupt request, the corresponding interrupt
flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT0 in GICR are set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical one to it. This flag is always cleared when INT0 is configured
as a level interrupt
Bit 5 - INTF2: External Interrupt Flag 2
When an event on the INT2 pin triggers an interrupt request, the corresponding interrupt
flag, INTF2 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT2 in GICR are set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical one to it.
Bits 4..0 - Res: Reserved Bits
These bits are reserved bits in the ATmega16 and always read as zero.
8-bit Timer / Counter 0 usage

Timer/Counter0 Control Register (TCCR0), Bits CS02-CS00

select Clock Source and Prescaler Value :
II: Atmega8 – Basic features

8-bit Timer / Counter0 usage

Timer/Counter0 Register (TCNT0) :

read/write, incremented per CLK cycle, overflow: 0xff

• A Reload-Value is used to fine-tune the interrupt interval

• Write Reload-Value to TCNT0 in the ISR

8-bit Timer / Counter0 usage

Timer/Counter Interrupt Mask Register (TIMSK) :

Bit 0 : Timer 0 interrupt enable
set 1 to enable timer 0 overflow interrupt ( + I-Bit in SREG)

Timer Interrupt Flag Register (TIFR) :

TOV0 indicates a Timer0 overflow, cleared by hardware when
the ISR is executed or by writing 1 to the flag
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