Subject: VLSI DESIGN

Topic: Brief Introduction to VLSI

DESIGN
- BY [Link] PRASANTH

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 CONTENTS

1. Introduction to VLSI
2. IC Fabrication Process
3. Different IC Technologies
4. MOS Transistor- Types- Modes
5. MOS Transistor as Switches

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 1. INTRODUCTION
 VLSI-Very Large scale Integration
 It is the process of designing, verifying, fabricating and testing of a
VLSI IC or CHIP
 VLSI had offered new opportunity to design circuits which were not
possible before with old circuits.
 PLD’S and Electronic Design Automation Tools have added many
advancements in VLSI Design.
 The concept of IC was conceived and demonstrated by JACK KILBY
of TEXAS INSTRUMENTS at Dallas of USA in the year 1958

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History
The integrated circuit or IC was put forth by Jack Kilby
at Texas Instruments
 Moore's law

In the year 1965 Gordon Moore Intel Co-Founder and Chairman

predicted that transistors would continue to shrink , allowing :

-- Doubled transistors density every 18-24 months

-- Doubled performance every 18-24 months

The period often quoted as "18 months

 2. IC Fabrication Process

 Oxidation: Oxidation is a process which converts silicon on the

wafer into silicon dioxide
 Etching: Etching is used to remove material selectively in order to
create patterns
 Diffusion: Doping is done by diffusion.


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  Photolithography: Selective Removal of oxide is done through
this.
 In this Process entire surface of oxide layer is coated with
photoresist. It is exposed to UV Rays. The region of photoresist that
is exposed to UV Radiation becomes soft and can be removed easily
.

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 Epitaxy: The Process of growing another single crystal on the top of
substrate is known as epitaxy.
 Metallization: it is to interconnect various components to form
desired IC. It is used to provide internal and external connections.

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 3. IC Technologies
 Bi-Polar- TTL,ECL
 MOS TECHNOLOGY CMOS-N-MOS, P-MOS
 Bi-CMOS( CMOS+ BJT FANOUT INCREASE)
 GaAS
 SiGe
Note: CMOS Fabrication: P-Well, N-Well, Twin-Tub, SOI

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 CMOS VS BI-CMOS

CMOS BI-CMOS
Low Static Power High Static Power
Dissipation Dissipation
High Input Impedance Low Input Impedance
High Package Density Low Package Density
Low Output Drive Current High Output Drive Current
Bi- Directional Uni- Directional

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 4. MOS TRANSISTORS

 Basically, there are two types of FET, they are JFET and MOSFET.
MOSFET stands for metal oxide semiconductor field effect
transistor, which is one of the most important devices used in
design and construction of integrated circuit for digital
computers.
 In the MOSFET, there is no direct electrical connection between the
gate terminal and the channel of the MOSFET which were present
in the JFET, this is due to the fact that MOSFET uses an
additional insulator layer of SiO2 which provides good
electrical isolation, this is the reason why the input impedance of
MOSFET is very high as compared to the JFET.
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 N-MOS TRANSISTOR

INSULATOR, PROVIDES
HIGH INPUT IMPEDANCE

HEAVILY DOPED N-TYPE

IMPURITIES

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 Symbols

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 Modes of Operation

 Depletion Mode: In this mode MOS Transistor working as a closed

switch.
 pre-existing channel
 Enhancement Mode: In this mode MOS Transistor working as a
Open Switch
 No Pre-Existing Channel Available.

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 MOS TRANSISTOR AS SWITCHES

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 Subject: VLSI DESIGN
Topic: BASIC ELECTRICAL
PROPERTIES
- BY [Link] PRASANTH

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 BASIC ELECTRICAL PROPERTIES

1. IDS VS VDS REALTIONSHIPS

2. THRESHOLD VOLTAGE
3. TRANSCONDUCTANCE
4. OUTPUT CONDUCTANCE
5. CHANNEL LENGTH MODULATION
6. FIGURE OF MERIT
7. BODY EFFECT
8. PASS TRANSISTOR LOGIC

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 1. IDS versus Voltage VDS
Relationships
 Non- Saturated Region:

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 Saturation Region

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 2. Threshold Voltage

 VGS required to accumulate sufficient [Link] mobile electrons in the

channel is called Vt.

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 3. Transconductance

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 4. O/P conductance

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 5. Channel Length Modulation

 Channel length of Mosfet is changed due to change in drain to

source voltage. This effect is called channel length modulation.

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 6. Figure of Merit

 It is a quantity used to characterize the performance of a

device comparative to other devices of similar kind.
 Figure of merit is defined as: ωo = gm/Cg
 Where gm is Trans conductance. Cg is gate capacitance.
 ωo = (μ/L2) (Vgs-Vt) = 1/ τsd … A fast ckt requires high gm, From
equation, switching speed depends on
 a) Carrier mobility b) Gate voltage (above threshold) c) Inversely
on square of channel length.

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 7. Body Effect

 Vsb as observed vertically upwards Vsb1=0 and

Vsb2=[Link] means that Vsb2 and Vsb1 are not same.
This variation of Vsb causes variation in threshold
voltage. i.e., Vt2>[Link] Variation of Vt due to
source to substrate voltage is called Body Effect.
 Summary of Body Effect
 • As Vsb increases threshold voltage VT increases.
 • Can cause a degradation in circuit performance

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 8. Pass Transistor Logic

 Pass characteristics:
 passing of voltage from drain ( or source)to source( or drain ) when device is ON
(via gate voltage)

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 Subject: VLSI DESIGN
Topic: MOS INVERTERS AND THEIR
CONFIGURATIONS
- BY [Link] PRASANTH

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 NMOS Inverter
 Vin=0N1Open Circuit, VOUT=Vdd
 Vin=1N2Shortcircuit,VOUT=0 RESTITIVE
 N2
Vin=Vdd/2 N1,N2Saturation LOAD
 If Vout=Vin then meeting point of
Input and output is Vinv.
 Vin=Vout=Vinv=0.5Vdd
N1

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 Output Characteristics

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 NMOS PMOS Vout

Region-1 OFF- ON-LINEAR Vdd/2

CUTOFF
Region-2 SATURATI NON- > VDD/2
ON SATURATION

Region-3 SATURATI SATURATION 0

ON
Region-4 LINEAR SATURATION <VDD/2
Region-5 LINEAR CUTOFF 0

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 Characteristics

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 BI_CMOS INVERTER

No discharge
path for base
current when
BJT IS IN OFF
CONDITION.

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 DESCRIPTION

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 Improved BI_CMOS INVERTER

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 DESCRIPTION

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 DETERMINATION OF PULL UP TO PULL DOWN RATIO
OF AN INVERTER DRIVEN BY ANOTHER INVERTER

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 Pull -Up to Pull-Down ratio for an nMOS
Inverter driven through one or more Pass
Transistors

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 ALTERNATE FORMS OF PULL UP LOADS
1. Load resistance RL :

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 2.
nMOS depletion mode transistor pull-up

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 nMOS enhancement mode pull-up:

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 Complementary transistor pull-up
(CMOS) :

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