بسم الله الرحمن الرحيم
Future university
Faculty Of Engineering
Computer Organization
+
ATop-Level View of Computer
Function and Interconnection
Prepared by: Duaa Mohammed
+
Computer Components
Contemporary computer designs are based on concepts
developed by John von Neumann at the Institute for
Advanced Studies, Princeton
Referred to as the von Neumann architecture and is
based on three key concepts:
Data and instructions are stored in a single read-write
memory
The contents of this memory are addressable by location,
without regard to the type of data contained there
Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next
Hardwired program
The result of the process of connecting the various
components in the desired configuration
+
Hardware
and Software
Approaches
Software
• A sequence of codes or instructions
• Part of the hardware interprets each Software
instruction and generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter
Components
• Module of general-purpose arithmetic and
logic functions
• I/O Components
• Input module
+ • Contains basic components for accepting
data and instructions and converting them
into an internal form of signals usable by
the system
• Output module
• Means of reporting results
Memory Memory buffer
address register (MBR) MEMORY
register (MAR) • Contains the data
• Specifies the to be written into
address in memory or
memory for the receives the data
next read or write read from
memory
MAR
I/O address I/O buffer
register register
(I/OAR) (I/OBR)
• Specifies a • Used for the
+ particular I/O exchange of data
device between an I/O
module and the
CPU MBR
+
Fetch Cycle
At the beginning of each instruction cycle the
processor fetches an instruction from memory
The program counter (PC) holds the address of the
instruction to be fetched next
The processor increments the PC after each
instruction fetch so that it will fetch the next
instruction in sequence
The fetched instruction is loaded into the instruction
register (IR)
The processor interprets the instruction and performs
the required action
Action Categories
• Data transferred • Data transferred
from processor to or from a
to memory or peripheral
from memory to device by
processor transferring
between the
processor and
an I/O module
Processo
Processo
r-
r-I/O
memory
Data
• An Control processin
instruction g
may specify • The processor
that the may perform
sequence of some arithmetic
execution be or logic
altered operation on
data
Table 3.1
Classes of Interrupts
+
I/O Function
I/O module can exchange data directly with the processor
Processor can read data from or write data to an I/O
module
Processor identifies a specific device that is controlled by a
particular I/O module
I/O instructions rather than memory referencing instructions
In some cases it is desirable to allow I/O exchanges to
occur directly with memory
The processor grants to an I/O module the authority to read
from or write to memory so that the I/O memory transfer can
occur without tying up the processor
The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
This operation is known as direct memory access (DMA)
The interconnection structure must support the
following types of transfers:
Memory
Processo I/O to I/O to or
to Processo
r to processo from
processo r to I/O
memory r memory
r
An I/O
module is
allowed to
exchange
data
Processor Processor directly
reads an Processor reads Processor with
instructio writes a data from sends memory
n or a unit unit of an I/O data to without
of data data to device via the I/O going
from memory an I/O device through
memory module the
processor
using
direct
memory
access
A communication Signals transmitted by
pathway connecting two any one device are
or more devices available for reception by
• Key characteristic is that it
is a shared transmission
all other devices attached
to the bus
Bus
medium • If two devices transmit during
the same time period their
signals will overlap and
Inte
rcon
become garbled
Typically consists of
multiple communication
Computer systems
contain a number of nect
different buses that
lines
• Each line is capable of
provide pathways
between components at
ion
transmitting signals various levels of the
representing binary 1 and computer system
binary 0 hierarchy
System bus The most common
• A bus that connects computer
major computer interconnection
components structures are based on
(processor, memory, the use of one or more
I/O) system buses
Data Bus
Data lines that provide a path for moving data among
system modules
May consist of 32, 64, 128, or more separate lines
The number of lines is referred to as the width of the
data bus
The number of lines determines how many bits can be
transferred at a time
The width of the data bus
is a key factor in
determining overall
system performance
+ Address Bus Control Bus
Used to designate the source or Used to control the access
destination of the data on the and the use of the data and
data bus address lines
If the processor wishes to read
a word of data from memory it
Because the data and
puts the address of the address lines are shared by
desired word on the address all components there must
lines be a means of controlling
their use
Width determines the maximum
possible memory capacity of the Control signals transmit both
system command and timing
information among system
Also used to address I/O ports
modules
The higher order bits are used
to select a particular module Timing signals indicate the
on the bus and the lower order validity of data and address
bits select a memory location information
or I/O port within the module
Command signals specify
