The revolution in a nutshell

2
Different Layers
Polysilicon

N-diffusion

P-diffusion

Metal

Contact
Design Rules
 Design rules are a set of geometrical specifications that
dictate the design of the layout masks
 A design rule set provides numerical values
 For minimum dimensions
 For minimum line spacings
 Design rules must be followed to insure functional
structures on the fabricated chip
 Design rules change with technological advances
•The physical mask layout of any circuit to be manufactured using a particular process
must conform to a set of geometric constraints or rules, which are generally called
layout design rules.

•These rules usually specify the minimum allowable line widths for physical objects on-
chip such as metal and polysilicon interconnects or diffusion areas, minimum feature
dimensions, and minimum allowable separations between two such features.

• If a metal line width is made too small, for example, it is possible for the line to break
during the fabrication process or afterwards, resulting in an open circuit.

•If two lines are placed too close to each other in the layout, they may form an unwanted
short circuit by merging during or after the fabrication process.

•The main objective of design rules is to achieve a high overall yield and reliability while
using the smallest possible silicon area, for any circuit to be manufactured with a
particular process.
 Why we need design rules?
 Design rules are supposed to prevent unworkable,
unreliable, or hard to implement constructs
 Design rules are introduced to preserve the integrity of
topological features on chip: to prevent separate, isolated
features from accidentally short circuiting, or thin
features from opening, or Contacts from slipping
outside the are a to be contacted
 Each piece of fabrication equipment used in the IC
manufacturing process has limited accuracy.
 We need rules to ensure that the inaccuracy in the
fabrication will not result in malfunction IC.
 There are limitations to the precision with which individual
processing steps can be performed
and with which separate processes can be aligned.
 Interface between designer and process engineer

 Guidelines for constructing process masks

 Allow translation of circuits (usually in stick diagram or

symbolic form) into actual geometry in silicon

 Compromise
 designer - tighter, smaller
 fabricator - controllable, reproducable
 Allow translation of circuits (usually in stick diagram or
symbolic form) into actual geometry in silicon
 Compromise
 designer - tighter, smaller
 fabricator - controllable, reproducable
3D Perspective

Polysilicon Aluminum
Design Rules Classification

 Minimum width
 Minimum spacing
 Surround
 Extension
Types of Design Rules
Scalable Design Rules
Lambda rules, which specify the layout constraints in terms of a
single parameter (λ) and, thus, allow linear, proportional scaling
of all geometrical constraints
Based on scalable “coarse grid” -λ(lambda)
The unit of lambda is micrometer
Idea: reduce λ value for each new process, but
keep rules the same
Key advantage: portable layout
Key disadvantage: not everything scales the same
Not used in “real life”
Scalable Design Rules
Absolute Design Rules(Non-scalable or Micron Rules)
Micron rules, in which the layout constraints such as
minimum feature sizes and minimum allowable feature
separations, are stated in terms of absolute dimensions in
micrometers
Based on absolute distances (e.g. 0.75μm)
Tuned to a specific process (details usually
proprietary)
Complex, especially for deep submicron
Layouts not portable
(Non-scalable or Micron Rules
Design Rules
LAYOUT OF NMOS AND PMOS
17
CMOS WELL RULE
SCMOS RULE FOR ACTIVE
 NMOS λ- DESIGN RULES
N + DIFFUSION MASK
SR. DESCRIPTION LAMDA
NO.
1 Diffusion Width 2

2 Diffusion Spacing 2
 IMPLANT MASK
SR. DESCRIPTION LAMDA
NO.
1 Implant Gate Overlap 1.5 or 2

2 Implant to enhancement 1.5

gate spacing
Depletion Transistor
We need depletion implant

An implant surrounding the Transistor by 2

Ensures that no part of the transistor remains in the

enhancement mode

A separation of 2 from the gate of an

enhancement transistor avoids affecting the 2

device.
BURRIED CONTACT MASK
SR. DESCRIPTION LAMDA
NO.
1 Burried contact to active device 2

2 Overlap in diffusion direction 2

3 Burried contact to Unrelated poly or 2

diffusion
4 Burried contact poly to unrelated poly 2
 Stick Diagrams
 A stick diagram is a cartoon of a layout.
 VLSI design aims to translate circuit concepts onto
silicon
 stick diagrams are a means of capturing topography
and layer information - simple diagrams
 Stick diagrams convey layer information through color
codes (or monochrome encoding)
 Stick diagrams are commonly used to represent the
topology (not the geometry) of CMOS integrated
circuits. With a little annotation (FET width and length)
they provide adequate information to guide layout and
mask generation.
 Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
NMOS and PMOS stick and layout encoding
PMOS stick encoding NMOS stick encoding

OR
OR

PMOS Layout encoding NMOS Layout encoding

OR
OR
 Vdd N-well
CMOS contact
Inverter

Vin Vout

Demarcation
line

Schematic Gnd
P-well
Stick diagram contact
 Vdd
Vdd

N-well

Vin
Vout
Vin Vout

Gnd Gnd
Implementation of Boolean Equation

 When there is a AND operation, put transistors in series

 When there is a OR operation, put transistors in parallel

Implementation of Boolean Equations using
CMOS Vdd
P-SIDE
(pull-up network)

Vou
t

N-SIDE
(pull-down network)
Implementation of NAND, NOR and Boolean
Equations using CMOS
 N-well
Stick Diagram
VDD
contact

A B

Vout

A
B

Gnd
P-well
contact
 Vdd

Layout Diagram
Vdd A B

A B

Vout Vout

A
A
B
B

Gnd

Gnd
2 I/P NOR GATE USING
CMOS LOGIC
2 I/P NOR GATE USING
CMOS LOGIC
Complex Boolean Equations
Complex Boolean Equations
Complex Boolean Equations
Complex Boolean Equations
 Y

W X

O/P

W Y

X
 VDD

Y Y

W X
W X

O/P

W Y
W
Y X
X

GND
 VDD
Draw circuit diagram
and stick diagram for C
the following
expression B
A

C
B D
 VDD

C C

B B
A A
D
D

O/P

A
A
C
C
B D B D

GND
Implementation of Inverter, NAND, NOR
and Boolean Equations using NMOS logic
NMOS Inverter
CMOS Inverter

Vin
 Stick Diagram

VDD

NMOS Inverter Implant

Vout

Buried
contact
Vin
Vin

Gnd
 VDD

VDD
Implant

NMOS Inverter

Buried
Vout contact

Vout

Vin
Vin
Vin

Gnd

Gnd
Implementation of NAND, NOR and Boolean
Equations using NMOS
NMOS logic
CMOS logic
Stick Diagram
VDD

Implant

Vout

Buried
contact
A

Gnd
 VDD

VDD Implant

Buried
Vout contact

Vout

A A

B B

Gnd

Gnd
 NMOS logic

CMOS logic
 VDD

Vout

A B

Gnd
 VDD

VDD Implant

Buried
contact
Vout

Vout

A B

A B

Gnd

Gnd
CMOS logic NMOS logic
 VDD

Vout

A B

D E C

Gnd
CMOS logic NMOS logic
 VDD

Vout

B C

D E A

Gnd
 VDD

Vout

O/P

W
W Y Y
X
X

Gnd
 VDD

Vout

A
A
C
C B D
B D
Gnd
When a transistor is formed?

Gate is formed where polySi crosses diffusion with thin oxide

between these layers.

Design rules
min. line width of polySi and diffusion 2
drain and source have min. length and width of 2
And
PolySi extends in the gate region…

The polySi of the gate extends 2 beyond the gate area on to the field
oxide to prevent the drain and source from shorting.

diffusion
short

• Diffusion Problems

no overlap overlap
Depletion Transistor
We need depletion implant

An implant surrounding the Transistor by 2

Ensures that no part of the transistor remains in the

enhancement mode

A separation of 2 from the gate of an

enhancement transistor avoids affecting the 2

device.
Depletion Transistor

Implants are separated by 2to prevent them from merging

2
Butting Contact

The gate and source of a depletion device can be connected by a method

known as butting contact. Here metal makes contact to both the diffusion
forming the source of the depletion transistor and to the polySi forming
this device’s gate.

Advantage:
No buried contact mask required and avoids associated
processing.
Butting Contact
Problem: Metal descending the hole has a tendency to fracture at
the polySi corner, causing an open circuit.
Metal

Insulating
Oxide
n+ n+

Gate Oxide PolySi

Buried Contact

It is a preferred method. The buried contact window defines the

area where oxide is to be removed so that polySi connects
directly to diffusion.
Contact Area must be a min. of 2*2to ensure adequate contact
area.

2
Contact Area

2
Buried Contact

The buried contact window surrounds this contact by in all directions to
avoid any part of this area forming a transistor.

Separated from its related transistor gate by  to prevent gate area from
being reduced.


Buried Contact

Here gate length is depend upon the alignment of the buried contact
mask relative to the polySi and therefore vary by .

PolySi
 2  Channel length 

Buried contact 2

Diffusion
Contact Cut
Contact cut – any gate: 2apart
Why? No contact to any part of the gate.

4

2
Contact Cut

Contact cut – contact cut: 2apart

Why? To prevent holes from merging.

2